Virtuoso AMS Environment User Guide

Variables for ams.env Files

maxErrors

Stops compilation if the number of errors reaches the specified maximum limit.

Syntax

amsDirect.vlog maxErrors int maxErrors

Example

amsDirect.vlog maxErrors int 50

Tells AMS Design Prep to compile Verilog files with the-errormax option. As a result, the generated command might look like this.

ncvlog -errormax 50

Virtuoso AMS Environment User Guide

Variables for ams.env Files

messages

Prints informational messages as the compiler runs.

Syntax

amsDirect.vlog messages boolean t | nil

Example

amsDirect.vlog messages boolean t

Tells AMS Design Prep to compile Verilog files with the-messages option. As a result, the generated command might look like this.

ncvlog -messages

Virtuoso AMS Environment User Guide

Variables for ams.env Files

modifyParamScope

Specifies that the AMS netlister treat atPar and dotPar expressions as pPar and iPar expressions, respectively.

Syntax

amsDirect modifyParamScope cyclic "no" | "warn" | "yes"

Description

The AMS netlister netlists one cellview at a time; it cannot see hierarchical dependencies defined or resolved outside of the current cellview. In addition, Verilog-AMS requires that passed parameters be resolved through the level of hierarchy immediately preceding the cellview to which the parameter applies. In other words, parameter passing cannot skip levels of the hierarchy. Because atPar and dotPar expressions allow parameters to be resolved in non-contiguous levels of the hierarchy, the AMS netlister does not support these expressions.

If you specify warn or yes, the AMS netlister treats atPar and dotPar expressions as pPar and iPar expressions, respectively, and generates a netlist. However, to avoid incorrect simulation results, you must ensure that the block instantiating the cell sets the instance parameters appropriately.

Virtuoso AMS Environment User Guide

Variables for ams.env Files

Example

Consider the following example of an inverter that employs atPar expressions. Assume that the nmos has defaults of ln=3u and wn=20u and that the pmos has defaults of lp=3u and wp=40u.

i1

L=atPar("lp")

W=atPar("wp")

L=atPar("ln")

W=atPar("wn")

i2

When this inverter is netlisted by the AMS netlister, it has an instance of an nmos and an instance of a pmos, each with parameters to be passed in:

pmos #(.W(wp), .L(lp)) i1 ( port_connections ); nmos #(.W(wn), .L(ln)) i2 ( port_connections );

The inverter module netlisted by the AMS netlister also has parameter statements for the parameters that are to supply values to the nmos and pmos instances:

parameter ln = 3u; parameter wn = 20u; parameter lp = 3u; parameter wp = 40u;

Virtuoso AMS Environment User Guide

Variables for ams.env Files

Now assume that this inverter is instantiated in a mid-level block, as follows:

The definition of the atPar expression allows the values for the parametersln, wn, lp, and wp to be provided at any level of the hierarchy above the mid-level block. In the preceding diagram, the values set in the higher-level block override the defaults defined in the nmos and pmos, and are used during the simulation:

■ln is set to 10 for the simulation

■wn is set to 5 for the simulation

■lp is set to 5 for the simulation

■wp is set to 10 for the simulation

This behavior is not possible when using Verilog-AMS. Verilog-AMS allows parameters to be passed from one level of hierarchy to the next level below, but the passing must be between contiguous levels. This behavior is identical to what is accomplished by pPar expressions. To be able to generate a netlist for the example, the AMS netlister must treat the atPar expressions as it does pPar expressions, expecting that any overriding of the parameters is done at the level of hierarchy immediately above.

Now assume that the AMS netlister is instructed to treat atPar expressions as it does pPar expressions. In this case, the higher-level block has an instance of the mid-level block, with the parameters set:

midlevel #(.ln(10u), .wn(5u), .lp(5u), .wp(10u)) i1 ( port_connections );

This instantiation assumes that the mid-level module has parameter declarations for the four parameters being passed in. However, the mid-level block does not reference these parameters at all, so no parameter declarations are printed by the AMS netlister.

The mid-level block has an instance of the inverter, passing no parameters at all:

inverter i1 ( port_connections );

Virtuoso AMS Environment User Guide

Variables for ams.env Files

Thus, when the nmos and pmos parameters are resolved, they are set to the defaults, because no values are passed in to override them:

■ln is set to 3 for the simulation

■wn is set to 20 for the simulation

■lp is set to 3 for the simulation

■wp is set to 40 for the simulation

Notice how these simulation values differ from those listed earlier. This example illustrates how simply instructing the AMS netlister to treat atPar expressions as pPar expressions might not produce the results you expect. To avoid incorrect results, you must ensure that parameters are passed in accordance with Verilog-AMS restrictions.