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Virtuoso AMS Environment User Guide

Variables for ams.env Files

iterInstExpFormat

Specifies the format to be used for the names of constituent elements generated by the expansion of an iterated instance.

Syntax

amsDirect.vlog iterInstExpFormat string "format"

Values

 

 

format

All characters, except those listed below, are printed exactly as

 

included in format. The following characters have the

 

indicated special meanings.

 

%b

Base name of the instance

 

%l (small L)

Left bound of the range

 

%r

Right bound of the range

 

%i

Index of the current iteration

 

%%

Prints the % character

The default value of format is %b_%i, which produces names like instbn_1, instbn_2, and so on, where instbn is the base name of the instance.

If a resulting name is illegal in Verilog-AMS, the name is mapped. If the mapped name clashes with the name of another object, the name undergoes collision mapping.

Example

amsDirect.vlog iterInstExpFormat string "%b_%l_%r_%i"

Tells AMS netlister to generate names that include the left and right bounds. For example, you have an iterated instance with the name scatstr. The names of the expanded instances are:

scatstr_1_3_1 scatstr_1_3_2 scatstr_1_3_3

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Variables for ams.env Files

language

Specifies the language to be used for netlists.

Syntax

amsDirect.prep language string "verilog"

Values

 

verilog

Specifies that the language to be used for netlists is

 

Verilog-AMS. This is the default.

Description

In this release, Verilog-AMS is the only supported language.

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Variables for ams.env Files

lexpragma

Enables processing of lexical pragmas.

Syntax

amsDirect.vlog lexpragma boolean t | nil

Values

 

t

Turns on processing of lexical pragmas.

nil

Turns of processing of lexical pragmas. This is the default

Description

Lexical pragmas are pragmas that can be associated with any Verilog or VHDL construct to indicate that translation/synthesis is turned off. The following pragmas are classified as lexical pragmas:

cadence translate_off and cadence translate_on (also: synopsys translate_off and synopsys translate_on)

cadence synthesis_off and cadence synthesis_on (also: synopsys synthesis_off and synopsys synthesis_on)

rtl_synthesis off and rtl_synthesis on

If you compile with the -lexpragma option, any HDL constructs between a translate_off/ synthesis_off pragma and a translate_on/synthesis_on pragma are treated as comments. For example, if the source code contains the following pragmas, ’define CI2CLKP 10 is treated as a comment.

’define CI2CLKP 512

//cadence translate_off ’define CI2CLKP 10

//cadence translate_on

If you use both -pragma and -lexpragma, lexical pragmas are processed with -lexpragma.

Example

amsDirect.vlog lexpragma boolean t

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Variables for ams.env Files

Tells AMS Design Prep to compile Verilog files with the-lexpragma option. As a result, the generated command might look like this.

ncvlog -lexpragma

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