Virtuoso AMS Environment User Guide

Preparing a Design for Simulation

If access permissions are set so that AMS Design Prep cannot write to the cds_globals module, the following user interfaces are affected:

Note these restrictions:

■AMS Design Prep cannot write the cds_globals information to a TMP file.

■The creation and updating of the cds_globals module is not subject to design management (DM) control, even when access to other objects in the design is controlled by a DM tool.

If the cds_globals module cannot be created or is not writable, you can specify a different location for the information. Choose AMS – Options – Global Design Data and enter a writable location in the Global Design Data Module pane.

The cds_globals Module

For some designs, such as those that combine HDL and CDBA cellviews, you need to understand the kinds of information placed in the cds_globals module, and what it means.

Do not change the name of the cds_globals module because it is automatically specified for simulation. (If your design contains no design variables or global signals, AMS Design Prep creates the cds_globals module as an empty module.)

Normally, the cds_globals module is written to the file

configLibName/cds_globals/configCellName_configView/verilog.vams

(However, you can change the location of the file. For more information, see“SettingOptions for Global Design Data” on page 211.)

Virtuoso AMS Environment User Guide

Preparing a Design for Simulation

For example, consider the following cds_globals module, which is located in a file named amsLib/cds_globals/top_config/verilog.vams. Notice the declarations of the global signals and the dynamicparam declaration of the design variable. For more information, see “Global Signals” on page 228 and“Design ariables”V on page 229.

//Verilog-AMS cds_globals module for top-level cell:

//amslib/top.

//Generated by AMS Design Prep.

//Cadence Design Systems, Inc.

‘include "disciplines.vams"

module cds_globals;

//Global Signals electrical \vdd! ; electrical \vss! ; electrical \gnd! ; ground \gnd! ;

//Design Variables dynamicparam real idc = 20u;

endmodule

It is not necessary for the discipline of every signal in the cds_globals module to be defined. As elsewhere in the design, the otherwise undefined disciplines are determined by the discipline resolution method that you use. For more information, see the “Discipline Resolution Methods” section in the “Mixed-Signal Aspects of Verilog-AMS” chapter, of the

Cadence Verilog-AMS Language Reference.

Creating Your Own cds_globals Module

You can create your own cds_globals module, overwriting the cds_globals module automatically created by AMS Design Prep. A cds_globals module created in this way is not overwritten by AMS Design Prep.

You might want to hand-create this module when

■You want a single or common module that is used by many designs instead of creating a cds_globals module for each configuration, which is what AMS Design Prep normally does. By creating a common module, you can avoid cluttering your library with cellviews that contain the same information.

■You want to declare global signals or design variables that are used in HDL cellviews but are not used in the schematic cellviews of your design.

Although Cadence does not recommend it, it is even possible to create many cds_globals modules, though each must be uniquely named. The AMS Designer flow only supports a single cds_globals module so if you have more than that, the modules must be added in the Additional arguments field of theElaborator pane in the AMS Options window.

Virtuoso AMS Environment User Guide

Preparing a Design for Simulation

Global Signals

A global signal is a signal that is available everywhere in the design hierarchy. AMS Design

Prep collects the global signals from each CDBA cellview of the design and stores the collected information in the cds_globals module. AMS Design Prep also provides a user interface that allows you to examine, change, and add to the global signals in your design.

For information on using the user interface, see “Specifying Global Signals” on page 213.

Unless you disable the automatic generation of the cds_globals module, AMS Design Prep regenerates the global signal information whenever global signals are added to or removed from the design.

Using Global Signals in Verilog (Digital) and Verilog-AMS HDL Modules

AMS Design Prep does not collect global signals from HDL cellviews. Consequently, if you want global signals in your Verilog (digital) and Verilog-AMS HDL cellviews—VHDL-AMS design units do not support using global signals—to interconnect with global signals in the netlists translated from schematic cellviews, you must use global signals from the cds_globals module in your Verilog (digital) and Verilog-AMS HDL cellviews. You do this by using out-of-module references to the global signals.

For example, consider the following cds_globals module produced by AMS Design Prep.

//Verilog-AMS netlist generated by the AMS netlister

//Cadence Design Systems, Inc.

‘include "disciplines.vams" ‘include "constants.vams"

module cds_globals;

//Global Signals electrical \vdd! ; electrical \vss! ; electrical \gnd! ; ground \gnd! ; wire signal1; ground signal2;

//Design Variables

dynamicparam real idc = 20u;

endmodule

You can refer to these global signals from within a Verilog-AMS module, for example, by using a hierarchical name such as cds_globals.signal1.

There are some complications produced by the fact that not all characters that are legal in CDBA modules are legal in Verilog-AMS modules. For example, a net name of vdd!, though legal in CDBA modules, is not allowed in Verilog-AMS and must be escaped. That is why, in the previous module, all of the signals defined with theelectrical discipline are escaped.

Virtuoso AMS Environment User Guide

Preparing a Design for Simulation

You must use the escaped names if you want to refer to these nets from within an HDL module. For example, you use a hierarchical name of "cds_globals.\vdd! " to refer to a net that in the CDBA module is simply vdd! (Note the space that terminates the escaped name).

The Default Global Signal of an Inherited Signal Expression

AMS Design Prep treats the default global signal of an inherited signal expression as a regular global signal in CDBA. The signal is also stored in the cds_globals module.

Design Variables

A design variable is a global variable that is available everywhere in the design hierarchy. AMS Design Prep collects the design variables found in each CDBA cellview of the design and declares them as dynamic parameters in the cds_globals module. AMS Design Prep also provides a user interface that allows you to examine, change, and add to the design variables in your design. For information on using the user interface, see “SpecifyingDesign Variables” on page 216.

Note: The VHDL-AMS language does not support out-of-module references, so you cannot set design variables within VHDL-AMS design units, nor can you, from within a VHDL-AMS design unit, directly access design variables used in other modules or design units.

A design variable can be referenced in the values of instance properties or AEL expressions.

(Note, however, that AMS Design Prep does not find design variables that are used in NLP expressions.) When converted to Verilog-AMS, a design variable can be referenced in the value of an expression via an out-of-module reference. For example, assume that sheetRes is a design variable declared in the cds_globals module with an expression such as

dynamicparam real sheetRes = 1.3 ;

Then you can refer to that value in a Verilog-AMS module with a statement such as

#(.r(cds_globals.sheetRes * area))

Virtuoso AMS Environment User Guide

Preparing a Design for Simulation

Virtuoso AMS Environment User Guide

11

Elaborating, Simulating, and Plotting

Results

This chapter contains the following sections:

■Specifying the Behavior of the Elaborator, Simulator, and Waveform Viewer on page 232

■Creating Probes on page 277

■Elaborating and Simulating on page 286

■Viewing Messages on page 289

■Plotting Waveforms After Simulation Ends on page 290