Virtuoso AMS Environment User Guide

4

Netlisting

The AMS netlister translates CDBA cellviews into Verilog® -AMS netlists. The output of a successful netlisting run is one or more files namedverilog.vams, each containing a valid

Verilog-AMS module that corresponds to a CDBA cellview. The netlister places each output file in the corresponding cellview directory.

As explained in this chapter, you can run the AMS netlister explicitly when necessary.

However, one of the strengths of the Virtuoso® AMS Designer flow is that you can set up the AMS netlister to run automatically whenever you check and save a schematic. When you run in this way, your design is always ready for simulation.

This chapter contains the following sections:

■Netlisting Modes Supported by the AMS Netlister on page 68

■Preparing Existing Analog Primitive Libraries for Netlisting on page 74

■Specifying the Behavior of the Netlister and Compilers on page 74

■Viewing the AMS Netlister Log on page 126

■Understanding the Output from the AMS Netlister on page 126

■How Inherited Connections Are Netlisted on page 127

■How Aliased Signals Are Netlisted on page 131

■How m-factors (Multiplicity Factors) Are Netlisted on page 132

■How Iterated Instances Are Netlisted on page 133

■Passing Model Names as Parameters on page 134

■Specifying Parameters to be Excluded from Netlisting on page 137

■Preparing to Netlist User-Defined Functions on page 140

■Ensuring that Floating Point Parameters Netlist Correctly on page 143