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Virtuoso AMS Environment User Guide

Designing for Virtuoso AMS Compliance

VHDL-AMS Component Declarations

You can simplify and speed up netlisting by using only one kind of component declaration methodology within your design. Mixing the package and inline methodologies within a design can force the AMS environment to reanalyze and renetlist cells that use inconsistent methodologies.

Properties

Your designs function most efficiently in the AMS environment if you use properties according to the guidelines in the following sections.

Properties to Avoid Completely

The properties listed in this section are not supported in the AMS environment and should not be used. If you use these properties, the AMS environment omits them from the netlist. This process increases the run time.

Property to avoid

Other Cadence netlisters that use the

property

 

 

 

hnlVerilogCDFdefparamList

Verilog

hnlVerilogHandleRCdata

Verilog

verilogFormatProc

Verilog

verilogView

Verilog

vhdlArchitectureName

VHDL

vhdlNetlistType

VHDL

vhdlPortType

VHDL

vhdlSignalKind

VHDL

 

 

Avoid the portOrder Property Unless Required by Special Circumstances

Unless you need the portOrder property to ensure that ports and buses are netlisted in a particular way, Cadence recommends not using the property.

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For information about how AMS Designer uses the portOrder property, see “amsDefinitionViews” on page 378.

Property to avoid unless required

Other Cadence netlisters that use the property

portOrder

VHDL and Verilog

 

 

Properties to Use Only in AMS Compatibility Mode

The properties listed in this section are supported only when you use the AMS compatibility mode. The AMS compatibility mode facilitates migration by instructing the netlister to support some of the properties used by other Verilog and VHDL netlisters.

Using the following properties when the AMS compatibility mode is not in effect slows down processing by the amount of time required to filter the properties out of the netlist.

Property to use only in AMS compatibility mode

Other Cadence netlisters that use the property

vhdlAttributeDefList

VHDL

vhdlComponentDecl

VHDL

vhdlFormalPortFuncName

VHDL

vhdlPackageComponents

VHDL

vhdlPackageNames

VHDL

 

 

Properties That Have No Special Meaning in the AMS Environment

The properties in this section have meaning for some netlisters, but have no special meaning in the AMS environment.

Property

Other Cadence netlisters that use the

property

 

 

 

algorithm

Verilog

c

Verilog

chargeDecay

Verilog

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Property

Other Cadence netlisters that use the

property

 

 

 

chargeStrength

Verilog

driveStrength

Verilog

High_Strength

Verilog

highThreshold

Verilog

length

Verilog

Low_Strength

Verilog

lowThreshold

Verilog

td

Verilog

technology

Verilog

tf

Verilog

tr

Verilog

tz

Verilog

width

Verilog

 

 

Properties Fully Supported by the AMS Environment

The properties in this section are fully supported in both the compatibility mode and the noncompatibility mode.

Property

Other Cadence netlisters that use the

property

 

 

 

hnlVerilogCellAuxData

Verilog

modelName

Verilog

netType

Verilog

nlAction="ignore"

VHDL and Verilog

vhdlActualPortFuncName

VHDL

vhdlComment

VHDL

vhdlDataType

VHDL

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Property

Other Cadence netlisters that use the

property

 

 

 

vhdlGenericDefList

VHDL

vhdlInitialValue

VHDL

vhdlResolveFunction

VHDL

vhdlScalarType

VHDL

vhdlVectorType

VHDL

 

 

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D

SKILL Functions and Customization

Variables

This appendix describes the Cadence SKILL languages functions and customization variables associated with the AMS environment. The included sections are:

SKILL Functions on page 616

Customization Variables on page 635

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