Virtuoso AMS Environment User Guide

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Designing for Virtuoso AMS Compliance

This appendix describes guidelines for creating schematic designs that the Virtuoso® AMS environment can handle efficiently. The consequences of not complying with these guidelines vary. In some cases, not complying with a guideline results in a netlist that is less readable or in the failure of downstream processes, such as cross-probing. In other cases, not complying with a guideline causes netlisting to fail.

The guidelines presented here are arranged in the following categories.

■Identifiers on page 604

■Terminals on page 606

■Buses on page 607

■Component Description Format on page 608

■Parameters on page 608

■Parameterized Cells on page 609

■VHDL-AMS Component Declarations on page 610

■Properties on page 610

Virtuoso AMS Environment User Guide

Designing for Virtuoso AMS Compliance

Identifiers

So that your design works efficiently with the Virtuoso AMS environment, ensure that the identifiers you use

■Follow the recommended syntax

■Map cleanly to the netlist languages you plan to use

■Are unique within your design

These guidelines are discussed in greater detail in the following sections.

Follow the Recommended Syntax for Identifiers

Use the following syntax for the basic_identifier when you create identifiers.

basic_identifier ::=

letter {[_] letter_or_digit}

letter_or_digit ::= letter

| digit

letter ::= a-z

digit ::=

0-9

For example, the following identifiers comply with this syntax.

an_identifier_name a_2nd_name

a_name2

However, the following identifiers donot comply with the syntax.

Ensure that Identifiers Map Cleanly to Netlist Languages

In addition to complying with the basic_identifier syntax, your identifiers should also map cleanly to the netlist languages that you plan to use. (In this release, the only supported

Virtuoso AMS Environment User Guide

Designing for Virtuoso AMS Compliance

netlist language is Verilog-AMS.) To meet the goal of mapping cleanly, follow these additional guidelines.

■Use only characters that are legal in the netlist languages you plan to use.

The AMS environment escapes illegal characters, resulting in a less readable netlist. For example, the identifiera&b appears in the netlist as \a&b followed by a space if your netlist language is Verilog-AMS; it appears as \a&b\ if your netlist language is VHDL-

AMS.

■Do not use names that are reserved words in the netlist languages you plan to use.

The AMS environment escapes any reserved word used as an identifier, resulting in a less readable netlist. For example, when used as an identifier, the reserved word nature appears in the netlist as \nature followed by a space if your netlist language is Verilog-AMS; it appears as \nature\ if your netlist language is VHDL-AMS.

Ensure that Identifiers Are Unique within Your Design

You should also ensure that every one of the instances, cells, terminals, parameters, and nets in your design has a unique identifier. As noted in the following tables, the consequences of not complying with this guideline vary from netlist failure to reduced cross-probing capabilities because the name in the netlist no longer matches the name in the schematic. The consequences also depend on the netlist language that you use.

VHDL-AMS: Handling of Non-Unique Identifiers