- •Contents
- •Preface
- •Related Documents
- •Typographic and Syntax Conventions
- •Creating HDL Modules for CDBA Cellviews
- •Creating HDL Data as You Save CDBA Cellviews
- •Creating HDL Data from Pre-existing CDBA Cellviews
- •Quick-Start Tutorial
- •The Circuit
- •AMS Designer Tools
- •Setting Up the Tutorial
- •Running from a Script
- •Running within the AMS Environment
- •Opening the Command Interpreter Window
- •Netlisting and Compiling
- •Elaborating and Simulating the Design
- •Summary
- •Setting Up the AMS Environment
- •Overview
- •The hdl.var File
- •The ams.env Files
- •AMS Designer Supports Design Management
- •Specifying the Text Editor to Use
- •Specifying Fonts for the Cadence Hierarchy Editor
- •Preparing to Use AMS Designer from the Hierarchy Editor
- •Netlisting
- •Netlisting Modes Supported by the AMS Netlister
- •Automatic Netlisting of a Cellview
- •Netlist Updating and Netlisting of Entire Designs
- •Netlisting from the UNIX Command Line
- •Library Netlisting
- •Netlisting of Cells in Response to Changes in CDF
- •Preparing Existing Analog Primitive Libraries for Netlisting
- •Specifying the Behavior of the Netlister and Compilers
- •Opening the AMS Options Windows
- •Setting Netlister Options from the Hierarchy Editor
- •Opening the CIW AMS Options Window
- •Setting Compiler Options
- •Viewing the AMS Netlister Log
- •Understanding the Output from the AMS Netlister
- •How Inherited Connections Are Netlisted
- •Inherited Signal Connections
- •Inherited Terminal Connections
- •Instance Values for Inherited Connections
- •Third-Party Tools and Other Cadence Tools
- •How Aliased Signals Are Netlisted
- •How m-factors (Multiplicity Factors) Are Netlisted
- •How Iterated Instances Are Netlisted
- •Passing Model Names as Parameters
- •Effect of the modelname, model, and modelName Parameters
- •Handling of the model* and componentName Parameters
- •Precedence of the model* and componentName Parameters
- •Specifying Parameters to be Excluded from Netlisting
- •Ignoring Parameters for Entire Libraries
- •Example: Specifying Parameters to Ignore
- •Ensuring that Floating Point Parameters Netlist Correctly
- •Working with Schematic Designs
- •Setting Schematic Rules Checker Options for AMS Designer
- •Creating Cellviews Using the AMS Environment
- •Preparing a Library
- •Creating the Symbol View
- •Using Blocks
- •Descend Edit
- •Inherited Connections
- •Global Signals in the Schematic Editor
- •Inherited Connections in a Hierarchy
- •How Net Expressions Evaluate
- •Net and Pin Properties
- •groundSensitivity and supplySensitivity Properties
- •Making Connect Modules Sensitive to Inherited Connection Values
- •Using External Text Designs
- •Overview of Steps for Using External Text Designs
- •Bringing Modules into a Cadence Library
- •Specifying the Working Library
- •Compiling into Libraries
- •Compiling into Temporary Libraries
- •Listing Compiled Modules
- •Using Text Blocks in Schematics
- •Using Modules Located in a Cadence Library
- •Preparing for Simulation
- •Using Analog Primitives
- •Using SPICE and Spectre Netlists and Subcircuits
- •Preparing to Use SPICE and Spectre Netlists and Subcircuits
- •Placing SPICE and Spectre Netlists and Subcircuits in a Schematic
- •Using Test Fixtures
- •Creating and Using a Textual Test Fixture
- •Creating a Textual Test Fixture
- •Using a Test Fixture
- •Example: Creating and Using a Test Fixture
- •Using Design Configurations
- •Ensuring HDL Design Unit Information Is Current
- •Preparing a Design for Simulation
- •Overview of AMS Design Prep
- •What AMS Design Prep Does to Prepare a Design for Simulation
- •When to Use AMS Design Prep
- •Specifying the Behavior of AMS Design Prep
- •Setting Options for Global Design Data
- •Specifying Global Signals
- •Specifying Design Variables
- •Specifying Model Files to Use During Elaboration
- •Running AMS Design Prep
- •The cds_globals Module
- •Global Signals
- •Design Variables
- •Setting Elaborator Options
- •Setting Simulator Options
- •Setting Waveform Selection Options
- •Creating Probes
- •Selecting Instances from the Virtuoso Schematic Editing Window
- •Selecting Buses
- •Selecting Instances from the Scope Navigator
- •Copying and Pasting Within Tables
- •Elaborating and Simulating
- •Viewing Messages
- •Plotting Waveforms After Simulation Ends
- •Starting the SimVision Waveform Viewer
- •Plotting Waveforms Selected on a Schematic (Direct Plot)
- •Using the amsdesigner Command
- •Examples
- •Producing Customized Netlists
- •Producing Customized Netlists
- •Identifying the Sections of a Netlist
- •Using ams.env Variables to Customize Netlists
- •Using Netlisting Procedures to Customize Netlists
- •Examples: Problems Addressed by Customized Netlists
- •Example: Adjusting Parameter Values to Account for Number of Fingers
- •Example: Using Symbols that Represent Verilog Test Code
- •Data Objects Supported for Netlisting
- •Netlister Object
- •Formatter Object
- •Cellview Object
- •Parameter Object
- •Instance Object
- •SKILL Functions Supported for Netlisting
- •Default Netlisting Procedures
- •Netlisting Helper Functions
- •Variables for ams.env Files
- •How AMS Designer Determines the Set of Variables
- •Why AMS Designer Uses ams.env Files, Not .cdsenv Files
- •List of ams.env Variables
- •Detailed Descriptions of ams.env Variables
- •aliasInstFormat
- •allowDeviantBuses
- •allowNameCollisions
- •allowSparseBuses
- •allowUndefParams
- •amsCompMode
- •amsDefinitionViews
- •amsEligibleViewTypes
- •amsExcludeParams
- •amsExpScalingFactor
- •amsLSB_MSB
- •amsMaxErrors
- •amsScalarInstances
- •amsVerbose
- •analogControlFile
- •bindCdsAliasLib
- •bindCdsAliasView
- •cdsGlobalsLib
- •cdsGlobalsView
- •checkAndNetlist
- •checkOnly
- •checktasks
- •compileAsAMS
- •compileExcludeLibs
- •compileMode
- •connectRulesCell
- •connectRulesCell2
- •connectRulesLib
- •connectRulesView
- •detailedDisciplineRes
- •discipline
- •excludeViewNames
- •hdlVarFile
- •headerText
- •ieee1364
- •ifdefLanguageExtensions
- •incdir
- •includeFiles
- •includeInstCdfParams
- •initFile
- •instClashFormat
- •iterInstExpFormat
- •language
- •lexpragma
- •logFileAction
- •logFileName
- •macro
- •maxErrors
- •messages
- •modifyParamScope
- •ncelabAccess
- •ncelabAnnoSimtime
- •ncelabArguments
- •ncelabCoverage
- •ncelabDelayMode
- •ncelabDelayType through ncelabMessages
- •ncelabMixEsc
- •ncelabModelFilePaths
- •ncelabNeverwarn through ncelabVipdelay
- •ncsimArguments
- •ncsimEpulseNoMsg through ncsimExtassertmsg
- •ncsimGUI
- •ncsimLoadvpi through ncsimStatus
- •ncsimTcl
- •ncsimUnbuffered through ncsimUseAddArgs
- •ncvhdlArguments
- •ncvlogArguments
- •ncvlogUseAddArgs
- •netClashFormat
- •netlistAfterCdfChange
- •netlistMode
- •netlistUDFAsMacro
- •neverwarn
- •noline
- •nomempack
- •nopragmawarn
- •nostdout
- •nowarn
- •paramDefVals
- •paramGlobalDefVal
- •pragma
- •processViewNames
- •prohibitCompile
- •runNcelab
- •runNcsim
- •scaddlglblopts
- •scaddltranopts
- •scale
- •scalem
- •scannotate
- •scapprox
- •scaudit
- •sccheckstmt
- •sccmin
- •sccompatible
- •scdebug
- •scdiagnose
- •scdigits
- •scerror
- •scerrpreset
- •scfastbreak
- •scgmin
- •scgmincheck
- •schomotopy
- •sciabstol
- •scic
- •scicstmt
- •scignshorts
- •scinfo
- •scinventory
- •sclimit
- •sclteratio
- •scmacromod
- •scmaxiters
- •scmaxnotes
- •scmaxrsd
- •scmaxstep
- •scmaxwarn
- •scmethod
- •scmodelevaltype
- •scmosvres
- •scnarrate
- •scnotation
- •scnote
- •scopptcheck
- •scpivabs
- •scpivotdc
- •scpivrel
- •scquantities
- •screadic
- •screadns
- •screlref
- •screltol
- •scrforce
- •scscale
- •scscalem
- •scscftimestamp
- •scscfusefileflag
- •scskipcount
- •scskipdc
- •scskipstart
- •scskipstop
- •scspeed
- •scstats
- •scstep
- •scstop
- •scstrobedelay
- •scstrobeperiod
- •sctemp
- •sctempeffects
- •sctitle
- •sctnom
- •sctopcheck
- •sctransave
- •scusemodeleval
- •scvabstol
- •scwarn
- •scwrite
- •simRunDirLoc
- •simVisScriptFile
- •status
- •templateFile
- •templateScript
- •timescale
- •update
- •use5xForVHDL
- •useDefparam
- •useNcelabNowarn
- •useNcelabSdfCmdFile
- •useNcsimNowarn
- •useNowarn
- •useScaddlglblopts
- •useScaddltranopts
- •useScic
- •useScreadic
- •useScreadns
- •useScwrite
- •useSimVisScriptFile
- •useProcessViewNamesOnly
- •verboseUpdate
- •vlogGroundSigs
- •vloglinedebug
- •vlogSupply0Sigs
- •vlogSupply1Sigs
- •wfDefaultDatabase
- •wfDefInstCSaveAll
- •wfDefInstCSaveLvl
- •wfDefInstSaveCurrents
- •wfDefInstSaveVoltages
- •wfDefInstVSaveAll
- •wfDefInstVSaveLvl
- •wfDefInstVSaveObjects
- •Updating Legacy SimInfo for Analog Primitives
- •The ams Fields
- •Special Handling of model, modelName, modelname, and componentName
- •Converting an Existing Analog Primitive Library
- •Designing for Virtuoso AMS Compliance
- •Terminals
- •Buses
- •Component Description Format
- •Parameters
- •Using Inherited Parameters
- •Using Cell Parameters
- •Parameterized Cells
- •VHDL-AMS Component Declarations
- •Properties
- •Properties to Avoid Completely
- •Avoid the portOrder Property Unless Required by Special Circumstances
- •Properties to Use Only in AMS Compatibility Mode
- •Properties That Have No Special Meaning in the AMS Environment
- •Properties Fully Supported by the AMS Environment
- •SKILL Functions
- •amsCheckCV
- •amsIsPresent
- •amsNetlist
- •amsProcessCellViews
- •amsUIOptionsForm
- •amsUIRunNetlisterForm
- •ddsCvtAMSTranslateCell
- •ddsCvtAMSTranslateLib
- •ddsCvtToolBoxAMS
- •vmsUpdateCellViews
- •Customization Variables
- •schHdlNotCreateDB
- •schHdlUseVamsForVerilog
- •vmsAnalysisType
- •vmsCreateMissingMasters
- •vmsNcvlogExecutable
- •vmsPortProcessing
- •vmsRunningInUI
- •vmsTemplateScript
- •vmsVerboseMsgLevel
- •Compiling Cadence-Provided Libraries
- •Purpose of the amsLibCompile Tool
- •Running the amsLibCompile Tool Manually
- •Example
Virtuoso AMS Environment User Guide
Using External Text Designs
Overview of Steps for Using External Text Designs
The AMS environment works most efficiently with modules that are available in Cadence
Library.Cell:View (5X) libraries. As a result, the strategy for using external text designs is to bring them into a library. A typical simplified series of steps looks like the following:
1.Specify the working library.
2.Use the -use5x option to compile modules into a library.
3.Create symbols for text modules that you plan to place in schematics.
4.Create a configuration that uses the text modules.
5.Run AMS Design Prep to generate a cds_globals module.
6.If necessary, edit the cds_globals module to add information about global variables and design variables found in the text modules.
7.Run the simulation.
These steps are described in more detail in the following sections.
Bringing Modules into a Cadence Library
Bringing modules into Cadence libraries does not mean copying modules into the libraries. Rather, it means establishing appropriate links from the cellview directory in the library to the original source information so that AMS Designer is aware of any changes to that source.
Specifying the Working Library
Some of the ncvlog commands discussed in this chapter compile modules into the working library. You must specify the working library by using the command
DEFINE WORK libraryName
in your hdl.var file.
If your design contains components from more than one library, define the working library to be the one that contains the top level of your design.
For more information, see “The hdl.arv File” on page 58.
April 2004 |
180 |
Product Version 5.3 |
Virtuoso AMS Environment User Guide
Using External Text Designs
If the access permissions for the working library do not allow writing, you can establish a corresponding temporary library that does allow writing. For more information, see
“Compiling intoemporaryT Libraries” on page 182.
Compiling into Libraries
To bring modules into the working library, compile them with the ncvlog or ncvhdl commands using the -use5x option. For example, the command
ncvlog -ams -use5x master.vams
adds a cell named master, with the default view name module, to the current working library.
The command
ncvhdl -v93 -ams -use5x daconv2.vhd
where the daconv2.vhd file contains specifications for an entity nameddaconv2 and an architecture named daconv2_behav, adds a cell named daconv2 with views named entity and daconv2_behav, to the current working library.
The module to be added to the library can be located in any directory. The following example illustrates this usage by specifying the path to the module.
ncvlog -ams -use5x /mnt4/lgp/master.vams
If the file you are working with contains more than one module, you can specify the module to be compiled. For example, the following command compiles the master1 Verilog-AMS module, which is located in the filemaster.vams.
ncvlog -ams -use5x -specificunit ncvlog_lib.master1:behavioral master.vams
This command adds a cell called master1, with a view called behavioral, to the ncvlog_lib library. The new behavioral view contains the master1 module from the master.vams file.
If you need to bring primitives into a 5X library system, compile them into a library that is used only by primitives. As described in “Using Modules Located in a Cadence Library” on
page 186, you need to use the Conversion Tool Box to convert primitive cells for use with AMS
Designer, but you must avoid converting non-primitive cells. Because the Conversion Tool
Box operates on entire libraries, the conversion process requires that the two kinds of cells be located in different libraries.
For detailed information about compiling into libraries, see Chapter 7 of Cadence
NC-Verilog Simulator Help and Chapter 6 of Cadence NC-VHDL Simulator Help.
April 2004 |
181 |
Product Version 5.3 |
Virtuoso AMS Environment User Guide
Using External Text Designs
Compiling into Temporary Libraries
If the access permissions for a library do not allow writing, you can establish a corresponding temporary (TMP) library that does allow writing. For more information, see “CadenceLibrary Structure”, in the Cadence Application Infrastructure User Guide.
By default, only derived data is allowed in TMP libraries. This means that if the non-writable library already contains a particular cellview, you can compile it into a TMP library. Even with an associated temporary library, though, you are not allowed to add new views or new cells to a non-writable library. That restriction presents no problem when you want to use only cells and views that already exist in the library. However, if you want to add a new cell or view to the library, perhaps to substitute a new behavioral view for an existing library schematic view, the derived data restriction becomes an obstacle.
To circumvent this restriction, Cadence provides the CDS_BIND_TMP_DD shell environment variable.
CDS_BIND_TMP_DD Shell Environment Variable
The CDS_BIND_TMP_DD variable allows cells and views to be created in TMP libraries, even when corresponding master data does not exist in the master library. Using this variable allows some Cadence tools to create cell and view master data in TMP libraries, a behavior that is otherwise prohibited. The CDS_BIND_TMP_DD variable is most useful when the master library is read-only and you need to make new cells or views available for use in your design.
The following table describes the effects of the CDS_BIND_TMP_DD variable values, which are case-insensitive. Setting the CDS_BIND_TMP_DD variable to a value other than those listed has the same effect as not setting the variable at all.
Value |
Effect |
|
|
both, cell, true, or |
Allow the creation, in a TMP library, of both new cells and new |
yes |
views, even when the corresponding master data does not exist in |
|
the master library. |
view |
Allows the creation, in a TMP library, of new views (only), even |
|
when the corresponding master data does not exist in the master |
|
library. |
|
|
For example, you have a read-only working library called amslib. You want to assign that library to a TMP library and you want to be able to create new cells in the TMP library. In the cds.lib file for the library, you add anASSIGN statement so the file contains the following statements:
April 2004 |
182 |
Product Version 5.3 |
Virtuoso AMS Environment User Guide
Using External Text Designs
DEFINE amslib ./AMS_lib/amsLib
ASSIGN amslib TMP /tmp/amslib_tmp
To permit the creation of new cells in the TMP library associated with the read-only amslib library, you set the environment variable on the command line.
setenv CDS_BIND_TMP_DD both
Then you use a command such as
ncvlog -ams -use5x -work amslib -view module compar6.vams
to compile the new compar6.vams module into the amslib TMP library.
Listing Compiled Modules
AMS Designer keeps a list of what has been compiled, which you can query with the UNIX command
ncls -library library_name
For example, assuming that you have a working library named amslib, the command
ncls -library amslib
might produce a list like the following.
ncls: 04.20-a001: (c) Copyright 1995-2002 Cadence Design Systems, Inc. module amslib.comparator:module (VST)
module amslib.comparator:module (SIG) <0x5d152f61> module amslib.comparator:module (SAM) <0x00000001> module amslib.comparator:module (SDB) architecture AMSLIB.DACONV:DACONV_BEHAV (AST)
architecture AMSLIB.DACONV:DACONV_BEHAV (SIG) <0x6210a27d> architecture AMSLIB.DACONV:DACONV_BEHAV (COD) <0x6210a27d> architecture AMSLIB.DACONV:DACONV_BEHAV (COD)
module amslib.elect_to_logic:module (VST)
module amslib.elect_to_logic:module (SIG) <0x3954d83b> module amslib.elect_to_logic:module (COD) <0x3954d83b> module amslib.elect_to_logic:module (SAM) <0x00000001> module amslib.elect_to_logic:module (SDB)
package AMSLIB.ELECTRICALSYSTEM (AST) package AMSLIB.ELECTRICALSYSTEM (COD) connect amslib.mixedsignal:connect (VST)
The first entry in this list, for example, says that in theamslib library, there is a cell called comparator, that has a view called module.
For more information on the ncls command, see the “ncls” section of the “Utilities” chapter, in the NC Verilog Simulator Help.
April 2004 |
183 |
Product Version 5.3 |