- •Contents
- •Preface
- •Related Documents
- •Typographic and Syntax Conventions
- •Creating HDL Modules for CDBA Cellviews
- •Creating HDL Data as You Save CDBA Cellviews
- •Creating HDL Data from Pre-existing CDBA Cellviews
- •Quick-Start Tutorial
- •The Circuit
- •AMS Designer Tools
- •Setting Up the Tutorial
- •Running from a Script
- •Running within the AMS Environment
- •Opening the Command Interpreter Window
- •Netlisting and Compiling
- •Elaborating and Simulating the Design
- •Summary
- •Setting Up the AMS Environment
- •Overview
- •The hdl.var File
- •The ams.env Files
- •AMS Designer Supports Design Management
- •Specifying the Text Editor to Use
- •Specifying Fonts for the Cadence Hierarchy Editor
- •Preparing to Use AMS Designer from the Hierarchy Editor
- •Netlisting
- •Netlisting Modes Supported by the AMS Netlister
- •Automatic Netlisting of a Cellview
- •Netlist Updating and Netlisting of Entire Designs
- •Netlisting from the UNIX Command Line
- •Library Netlisting
- •Netlisting of Cells in Response to Changes in CDF
- •Preparing Existing Analog Primitive Libraries for Netlisting
- •Specifying the Behavior of the Netlister and Compilers
- •Opening the AMS Options Windows
- •Setting Netlister Options from the Hierarchy Editor
- •Opening the CIW AMS Options Window
- •Setting Compiler Options
- •Viewing the AMS Netlister Log
- •Understanding the Output from the AMS Netlister
- •How Inherited Connections Are Netlisted
- •Inherited Signal Connections
- •Inherited Terminal Connections
- •Instance Values for Inherited Connections
- •Third-Party Tools and Other Cadence Tools
- •How Aliased Signals Are Netlisted
- •How m-factors (Multiplicity Factors) Are Netlisted
- •How Iterated Instances Are Netlisted
- •Passing Model Names as Parameters
- •Effect of the modelname, model, and modelName Parameters
- •Handling of the model* and componentName Parameters
- •Precedence of the model* and componentName Parameters
- •Specifying Parameters to be Excluded from Netlisting
- •Ignoring Parameters for Entire Libraries
- •Example: Specifying Parameters to Ignore
- •Ensuring that Floating Point Parameters Netlist Correctly
- •Working with Schematic Designs
- •Setting Schematic Rules Checker Options for AMS Designer
- •Creating Cellviews Using the AMS Environment
- •Preparing a Library
- •Creating the Symbol View
- •Using Blocks
- •Descend Edit
- •Inherited Connections
- •Global Signals in the Schematic Editor
- •Inherited Connections in a Hierarchy
- •How Net Expressions Evaluate
- •Net and Pin Properties
- •groundSensitivity and supplySensitivity Properties
- •Making Connect Modules Sensitive to Inherited Connection Values
- •Using External Text Designs
- •Overview of Steps for Using External Text Designs
- •Bringing Modules into a Cadence Library
- •Specifying the Working Library
- •Compiling into Libraries
- •Compiling into Temporary Libraries
- •Listing Compiled Modules
- •Using Text Blocks in Schematics
- •Using Modules Located in a Cadence Library
- •Preparing for Simulation
- •Using Analog Primitives
- •Using SPICE and Spectre Netlists and Subcircuits
- •Preparing to Use SPICE and Spectre Netlists and Subcircuits
- •Placing SPICE and Spectre Netlists and Subcircuits in a Schematic
- •Using Test Fixtures
- •Creating and Using a Textual Test Fixture
- •Creating a Textual Test Fixture
- •Using a Test Fixture
- •Example: Creating and Using a Test Fixture
- •Using Design Configurations
- •Ensuring HDL Design Unit Information Is Current
- •Preparing a Design for Simulation
- •Overview of AMS Design Prep
- •What AMS Design Prep Does to Prepare a Design for Simulation
- •When to Use AMS Design Prep
- •Specifying the Behavior of AMS Design Prep
- •Setting Options for Global Design Data
- •Specifying Global Signals
- •Specifying Design Variables
- •Specifying Model Files to Use During Elaboration
- •Running AMS Design Prep
- •The cds_globals Module
- •Global Signals
- •Design Variables
- •Setting Elaborator Options
- •Setting Simulator Options
- •Setting Waveform Selection Options
- •Creating Probes
- •Selecting Instances from the Virtuoso Schematic Editing Window
- •Selecting Buses
- •Selecting Instances from the Scope Navigator
- •Copying and Pasting Within Tables
- •Elaborating and Simulating
- •Viewing Messages
- •Plotting Waveforms After Simulation Ends
- •Starting the SimVision Waveform Viewer
- •Plotting Waveforms Selected on a Schematic (Direct Plot)
- •Using the amsdesigner Command
- •Examples
- •Producing Customized Netlists
- •Producing Customized Netlists
- •Identifying the Sections of a Netlist
- •Using ams.env Variables to Customize Netlists
- •Using Netlisting Procedures to Customize Netlists
- •Examples: Problems Addressed by Customized Netlists
- •Example: Adjusting Parameter Values to Account for Number of Fingers
- •Example: Using Symbols that Represent Verilog Test Code
- •Data Objects Supported for Netlisting
- •Netlister Object
- •Formatter Object
- •Cellview Object
- •Parameter Object
- •Instance Object
- •SKILL Functions Supported for Netlisting
- •Default Netlisting Procedures
- •Netlisting Helper Functions
- •Variables for ams.env Files
- •How AMS Designer Determines the Set of Variables
- •Why AMS Designer Uses ams.env Files, Not .cdsenv Files
- •List of ams.env Variables
- •Detailed Descriptions of ams.env Variables
- •aliasInstFormat
- •allowDeviantBuses
- •allowNameCollisions
- •allowSparseBuses
- •allowUndefParams
- •amsCompMode
- •amsDefinitionViews
- •amsEligibleViewTypes
- •amsExcludeParams
- •amsExpScalingFactor
- •amsLSB_MSB
- •amsMaxErrors
- •amsScalarInstances
- •amsVerbose
- •analogControlFile
- •bindCdsAliasLib
- •bindCdsAliasView
- •cdsGlobalsLib
- •cdsGlobalsView
- •checkAndNetlist
- •checkOnly
- •checktasks
- •compileAsAMS
- •compileExcludeLibs
- •compileMode
- •connectRulesCell
- •connectRulesCell2
- •connectRulesLib
- •connectRulesView
- •detailedDisciplineRes
- •discipline
- •excludeViewNames
- •hdlVarFile
- •headerText
- •ieee1364
- •ifdefLanguageExtensions
- •incdir
- •includeFiles
- •includeInstCdfParams
- •initFile
- •instClashFormat
- •iterInstExpFormat
- •language
- •lexpragma
- •logFileAction
- •logFileName
- •macro
- •maxErrors
- •messages
- •modifyParamScope
- •ncelabAccess
- •ncelabAnnoSimtime
- •ncelabArguments
- •ncelabCoverage
- •ncelabDelayMode
- •ncelabDelayType through ncelabMessages
- •ncelabMixEsc
- •ncelabModelFilePaths
- •ncelabNeverwarn through ncelabVipdelay
- •ncsimArguments
- •ncsimEpulseNoMsg through ncsimExtassertmsg
- •ncsimGUI
- •ncsimLoadvpi through ncsimStatus
- •ncsimTcl
- •ncsimUnbuffered through ncsimUseAddArgs
- •ncvhdlArguments
- •ncvlogArguments
- •ncvlogUseAddArgs
- •netClashFormat
- •netlistAfterCdfChange
- •netlistMode
- •netlistUDFAsMacro
- •neverwarn
- •noline
- •nomempack
- •nopragmawarn
- •nostdout
- •nowarn
- •paramDefVals
- •paramGlobalDefVal
- •pragma
- •processViewNames
- •prohibitCompile
- •runNcelab
- •runNcsim
- •scaddlglblopts
- •scaddltranopts
- •scale
- •scalem
- •scannotate
- •scapprox
- •scaudit
- •sccheckstmt
- •sccmin
- •sccompatible
- •scdebug
- •scdiagnose
- •scdigits
- •scerror
- •scerrpreset
- •scfastbreak
- •scgmin
- •scgmincheck
- •schomotopy
- •sciabstol
- •scic
- •scicstmt
- •scignshorts
- •scinfo
- •scinventory
- •sclimit
- •sclteratio
- •scmacromod
- •scmaxiters
- •scmaxnotes
- •scmaxrsd
- •scmaxstep
- •scmaxwarn
- •scmethod
- •scmodelevaltype
- •scmosvres
- •scnarrate
- •scnotation
- •scnote
- •scopptcheck
- •scpivabs
- •scpivotdc
- •scpivrel
- •scquantities
- •screadic
- •screadns
- •screlref
- •screltol
- •scrforce
- •scscale
- •scscalem
- •scscftimestamp
- •scscfusefileflag
- •scskipcount
- •scskipdc
- •scskipstart
- •scskipstop
- •scspeed
- •scstats
- •scstep
- •scstop
- •scstrobedelay
- •scstrobeperiod
- •sctemp
- •sctempeffects
- •sctitle
- •sctnom
- •sctopcheck
- •sctransave
- •scusemodeleval
- •scvabstol
- •scwarn
- •scwrite
- •simRunDirLoc
- •simVisScriptFile
- •status
- •templateFile
- •templateScript
- •timescale
- •update
- •use5xForVHDL
- •useDefparam
- •useNcelabNowarn
- •useNcelabSdfCmdFile
- •useNcsimNowarn
- •useNowarn
- •useScaddlglblopts
- •useScaddltranopts
- •useScic
- •useScreadic
- •useScreadns
- •useScwrite
- •useSimVisScriptFile
- •useProcessViewNamesOnly
- •verboseUpdate
- •vlogGroundSigs
- •vloglinedebug
- •vlogSupply0Sigs
- •vlogSupply1Sigs
- •wfDefaultDatabase
- •wfDefInstCSaveAll
- •wfDefInstCSaveLvl
- •wfDefInstSaveCurrents
- •wfDefInstSaveVoltages
- •wfDefInstVSaveAll
- •wfDefInstVSaveLvl
- •wfDefInstVSaveObjects
- •Updating Legacy SimInfo for Analog Primitives
- •The ams Fields
- •Special Handling of model, modelName, modelname, and componentName
- •Converting an Existing Analog Primitive Library
- •Designing for Virtuoso AMS Compliance
- •Terminals
- •Buses
- •Component Description Format
- •Parameters
- •Using Inherited Parameters
- •Using Cell Parameters
- •Parameterized Cells
- •VHDL-AMS Component Declarations
- •Properties
- •Properties to Avoid Completely
- •Avoid the portOrder Property Unless Required by Special Circumstances
- •Properties to Use Only in AMS Compatibility Mode
- •Properties That Have No Special Meaning in the AMS Environment
- •Properties Fully Supported by the AMS Environment
- •SKILL Functions
- •amsCheckCV
- •amsIsPresent
- •amsNetlist
- •amsProcessCellViews
- •amsUIOptionsForm
- •amsUIRunNetlisterForm
- •ddsCvtAMSTranslateCell
- •ddsCvtAMSTranslateLib
- •ddsCvtToolBoxAMS
- •vmsUpdateCellViews
- •Customization Variables
- •schHdlNotCreateDB
- •schHdlUseVamsForVerilog
- •vmsAnalysisType
- •vmsCreateMissingMasters
- •vmsNcvlogExecutable
- •vmsPortProcessing
- •vmsRunningInUI
- •vmsTemplateScript
- •vmsVerboseMsgLevel
- •Compiling Cadence-Provided Libraries
- •Purpose of the amsLibCompile Tool
- •Running the amsLibCompile Tool Manually
- •Example
Virtuoso AMS Environment User Guide
Netlisting
Netlisting Modes Supported by the AMS Netlister
The AMS netlister provides several ways to netlist cellviews:
■Automatic netlisting, where an application-specific operation (such asCheck and Save in the Virtuoso Schematic Editor) triggers netlisting of the cellview being saved
■Netlist updating and netlisting of entire designs using the Cadence hierarchy editor
■Netlisting from the UNIX command line
■Library netlisting, using a menu command in the CIW to netlist an entire library, all the views of a cell, or a single cellview
■Netlisting of cells in response to changes in CDF
The following sections describe each of these methods in more detail and explain how to use them.
Automatic Netlisting of a Cellview
This method is perhaps the most likely to be used in day-to-day production work, because netlisting is transparent, occurring automatically whenever you save a CDBA view that has valid connectivity. When you use this method and specify that both netlisting and compiling take place automatically, you always have the information required so the next tool in the flow, AMS Design Prep or the AMS simulator, can run quickly.
To use this method,
1. Choose Tools – AMS – Options in the CIW to display the AMS Options window.
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2. Select Check and Save in the Categories field.
3.Select what you want the AMS netlister to do when you check and save a CDBA cellview.
You can choose to have the netlister check, netlist, and compile the cellview.
Note: If Generate AMS netlist is disabled, the AMS netlister removes any netlist previously created by the netlister for the cellview being checked and saved. This behavior continues even when the AMS tools are disabled. This process of removing existing netlists ensures that you do not inadvertently simulate an out-of-date netlist.
4.If necessary, select other choices in the Categories field and set the options that control the AMS netlister. For more information, see “Specifyingthe Behavior of the Netlister and Compilers” on page 74.
5.Click OK or Apply to save your settings.
At this point you are ready to work with the CDBA data. For example, you use Virtuoso Schematic Editor to create or edit schematic views, then use the Check and Save command. In response, the AMS netlister runs automatically, creating a Verilog-AMS netlist in the cellview directory of your saved schematic view. The newly created netlist is available
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to all users of the block: None of the users need to recreate the netlist unless the block changes.
Netlist Updating and Netlisting of Entire Designs
In this method, the AMS netlister runs under the control of AMS Design Prep. AMS Design
Prep is a Cadence hierarchy editor plug-in that operates on the design configuration. This is the easiest method to use when you are primarily interested in ensuring that all the cellviews used in a design have up-to-date netlists.
For guidance on using AMS Design Prep, see Chapter 10, “Preparing a Design for Simulation.”
Netlisting from the UNIX Command Line
This method allows you to netlist an entire library, all the views of a cell, or a single cellview without starting the graphical user interface. Instead you use the amsdirect command, which has the following syntax.
amsdirect_command ::=
amsdirect -LIb libName [ -Cell cellName ] [ -VIew viewName ] [ -VERIlog ] [ -Env envFileName ] [ -LOg logFileName ] [ -Incremental ] [ -Help ] [ -VERSion ]
The following table describes the amsdirect command options.
amsdirect Option |
Effect |
|
|
-LIb libName |
Specifies the library containing the cellviews that you want to |
|
translate from CDBA to Verilog-AMS netlists. If you do not specify |
|
a cell with the -Cell option, the AMS netlister translates eligible |
|
views for every cell in the library. |
-Cell cellName |
Specifies the cell containing the cellviews that you want to |
|
translate from CDBA to Verilog-AMS netlists. If you do not specify |
|
a view with the -VIew option, the AMS netlister translates each |
|
view type listed on the amsEligibleViewTypes variable in the |
|
ams.env file. |
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amsdirect Option |
Effect |
|
|
-VIew viewName |
Specifies the cellview name that you want to translate from CDBA |
|
to a Verilog-AMS netlist. The type of the cellview must be one of: |
|
schematic, symbolic, maskLayout, or netlist but the |
|
name of the cellview can be any legal name. If you do not specify |
|
a view name, the AMS netlister netlists each view type listed on |
|
the amsEligibleViewTypes variable in the ams.env file. |
-VERIlog |
Tells the AMS netlister to produce Verilog-AMS netlists for the |
|
processed CDBA cellviews. This option takes precedence over |
|
the checkOnly and checkAndNetlist variables, whose |
|
settings in the ams.env file otherwise determine the behavior. If |
|
both variables are set to nil and you do not use the -VERIlog |
|
option, the AMS netlister does nothing. |
-Env envFileName |
Tells the AMS netlister to read the ams.env variables in the |
|
envFileName file and to use them to overlay the base set of |
|
ams.env variables. For information about how the base set of |
|
variables is determined, see “How AMS Designer Determines the |
|
Set of Variables” on page 360. |
|
Note: If envFileName is read while the base set is being |
|
determined, the -Env option has no effect. |
-LOg logFileName |
Tells the AMS netlister to write messages to logFileName. The |
|
-LOg option takes precedence over the logFileName variable |
|
used in ams.env files. |
|
If logFileName is an absolute path, the log file is written to |
|
logFileName. |
|
If logFileName is a relative path and |
|
CDS_LOG_PATH is null, logFileName is placed in the |
|
current directory. |
|
CDS_LOG_PATH is non-null, the value of CDS_LOG_PATH |
|
is prepended to logFileName. |
|
For more information about specifying the log file, see |
|
“logFileName” on page 421. |
-Incremental |
Tells the AMS netlister to netlist only new or revised cellviews. |
-Help |
Returns a brief description of the amsdirect command and its |
|
options. |
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