Virtuoso AMS Environment User Guide

Preparing a Design for Simulation

Overview of AMS Design Prep

Virtuoso® AMS Design Prep prepares a design for simulation by creating Verilog® -AMS netlists for CDBA cellviews in your design. This preparation ensures that the Verilog-AMS netlist and compiled representations generated from a CDBA cellview are up-to-date. View types that are eligible for netlisting are schematic, symbolic, maskLayout, and netlist.

When AMS Design Prep prepares a CDBA cellview for simulation, it calls the AMS netlister, which produces a netlist file calledverilog.vams. AMS Design Prep also creates the cds_globals module, which contains global signals and design variables information.

What AMS Design Prep Does to Prepare a Design for Simulation

AMS Design Prep performs the following tasks to prepare a design for simulation:

■Traverses the design configuration using the hierarchy editor traversal engine.

■Calls the AMS netlister to generate netlists for CDBA cellviews. See Chapter 4, “Netlisting” for more information.

■Calls ncvlog or ncvhdl to compile netlists and other HDL views. See “compileMode” on page 398 for details about how the compilers determine which views to compile.

■Enables the use of CDBA global signals by creating a cds_globals module if global signals exist in the design. The user interface that you use to edit global signals is discussed later in this chapter.

■Enables the efficient use of multiple electrical ground references by taking advantage of the Verilog-AMS ground declaration. Each CDBA global signal that is specified as an electrical ground reference is associated with the Verilog-AMS global ground reference node.

■Enables the use of design variables by collecting all design variables in the design hierarchy, provides a user interface that you can invoke from the AMS plug-in menu in the Cadence hierarchy editor so you can edit their values, and creates dynamicparam statements in the cds_globals module. See “Specifying Design ariables”V on

page 216 for more information on the AMS Design Variables user interface.

■Allows re-netlisting and re-compilation of the entire design to ensure consistency. You can re-netlist all CDBA cellviews and re-compile all HDL units used in the design hierarchy. See “Specifying the Behavior of AMS Design Prep” on page 211 for more information.