Virtuoso AMS Environment User Guide

2

Quick-Start Tutorial

The Virtuoso® AMS environment and simulator work together to enable you to netlist, compile, elaborate, and simulate a circuit that contains analog, digital, and mixed-signal components. The AMS environment consists of the AMS netlister and AMS Design Prep. The former translates CDBA cellviews in your design to Verilog® -AMS netlists, and the latter prepares your design for simulation by letting you manage the global signals and design variables in your design and by ensuring that the netlists are up to date and compiled for elaboration.

In this tutorial, you use the AMS environment and simulator to netlist, compile, elaborate, and simulate the top schematic, which contains analog, digital, and mixed-signal components. If you are interested in the operation of the circuit components, read the next section.

Otherwise, skip ahead to “AMS Designerools”T on page 26.

The Circuit

The top object used in this tutorial is an 8-bit successive approximation A/D converter. (The schematic is shown on page 30.) At the top level, there are six blocks: two analog, two digital (one Verilog, one VHDL), and two mixed-signal (one Verilog-AMS, one VHDL-AMS).

The signalSrc block instantiates a Spectre primitive that provides the reference signal. The global supplies are defined usinganalogLib primitives for the positive and negative rails.

Virtuoso AMS Environment User Guide

Quick-Start Tutorial

The samplehold block is a Verilog-AMS module that has both analog and mixed-signal inputs and an analog output. There are no connection modules (interface elements used to connect digital and analog domains) for this block because each port connects to a port of the same domain.

The vhdl_clock block is a VHDL clock that provides the clock signal for the successive approximation register (SAR) block, sareg.

The daconv block is a VHDL-AMS 8-bit D/A block. This block reads the digital output of sareg and converts it to an analog signal that is input into the comparator for comparison to the reference signal. This is a mixed-signal block, but no connection modules are needed because its ports are all connected to ports of the same domain.

The comparator block is a Verilog-A block (or a Verilog-AMS netlist) that compares the reference signal after it is sampled to the converted digital output from sareg via daconv to see if conversion has occurred. Because the output of the comparator connects to a digital port on sareg, a connection module is needed for simulation.

Therefore, sareg is a Verilog block that connects with

■A VHDL block, vhdl_clock

■A VHDL-AMS block, daconv, via the digital ports

■A Verilog-A block (or Verilog-AMS netlist), comparator, where a connection module is needed

AMS Designer Tools

This tutorial describes how to use the following tools:

■Command Interpreter Window (CIW)

■Cadence hierarchy editor

■AMS netlister

■AMS compiler: ncvlog, ncvhdl

■AMS Design Prep

■AMS elaborator: ncelab

■AMS simulator: ncsim version LDV5.0 or later (using SimVision windows)

Virtuoso AMS Environment User Guide

Quick-Start Tutorial

Setting Up the Tutorial

Before you can run this tutorial, you need to set up the files and libraries. To do so,

1. Follow the instructions in the README file to set up the tutorial directories.

your_install_dir/tools/dfII/samples/tutorials/AMS/README

where your_install_dir is the Custom Integrated Circuits (CIC) software installation.

2. Go to the directory where your copy of the tutorial is located.

Running from a Script

In this section of the tutorial, you run a script that compiles, elaborates, and simulates the design using the textual descriptions of the components. This exercise illustrates how you can use the AMS simulator without using the AMS environment.

1.Use a viewing tool, such as vi, to examine the contents of the runBehavioral script. It looks like this:

#!/bin/csh -f

echo ""

echo " Compiling all analog and digital modules " echo " for an all behavioral simulation. "

echo ""

cd AMS_lib

rm -f amsLib/*.pak -exec rm {} \; compile *.vams

compilevhdl daconv.vhd

cd ../digitalLib

rm -f diglib/*.pak -exec rm {} \; compile *.v

compile *.vams

cd ..

echo ""

echo " Elaborating TEXT ONLY design. " echo ""

echo " top:module and comparator:module" echo ""

##############################

# Elab of TEXT ONLY design #

##############################

ncelab -timescale 1ns/100ps -discipline logic top:module mixedsignal:connect -nowarn DLCRDB

echo " Launching the Virtuoso AMS simulator."

ncsim top -amslic -ANALOGCONTROL top.scs -gui -input demo.tcl