Virtuoso AMS Environment User Guide

5

Working with Schematic Designs

One of the AMS Designer flows allows you to create a Verilog® -AMS netlist for each cellview you save using the Virtuoso® Schematic Editor. If you are familiar with the schematic editor, you already know most of what is required to take advantage of the AMS Designer capabilities. This chapter briefly reviews some of the features of the schematic editor: for complete information, see the Virtuoso Schematic Editor User Guide.

This chapter contains the following sections:

■Setting Schematic Rules Checker Options for AMS Designer on page 150

■Creating Cellviews Using the AMS Environment on page 152

■Inherited Connections on page 167

■Net and Pin Properties on page 172

Virtuoso AMS Environment User Guide

Working with Schematic Designs

Setting Schematic Rules Checker Options for AMS Designer

You use the Setup Schematic Rules Checks form to specify the checking that occurs when you check and save a schematic. For AMS Designer, the checks can give you feedback regarding CDBA-to-Verilog-AMS translation without having to generate a netlist. By default, this feature is not enabled.

After you set these rules and enable the checks, they are run by any of the following commands: Design – Check and Save, Check – Current Cellview, Check – Hierarchy.

To set up the Schematic Rules Checker (SRC) rules,

1.From the Virtuoso Schematic Editing window, choose Options – Check Rules Setup. The Setup Schematic Rules Checks form appears.

Virtuoso AMS Environment User Guide

Working with Schematic Designs

2. Click AMS to open the pane for the AMS Designer checks.

3.To enable the AMS checks, select yes for the Run AMS Checks field.

4.If necessary, change the severity levels for the Verilog AMS Checks.

For more information about these checks, see the following references.