Virtuoso AMS Environment User Guide

Designing for Virtuoso AMS Compliance

VHDL-AMS: Handling of Non-Unique Identifiers, continued

Terminals

Your designs should comply with the following guidelines for terminals.

■Every cellview of a cell should use the same set of terminals.

Following this general guideline facilitates cellview switching. However, the minimum requirement is that at least every connected terminal in a symbol must be defined in the switched view. In the switched view, you can have additional defined terminals that do not appear in the symbol view.

Virtuoso AMS Environment User Guide

Designing for Virtuoso AMS Compliance

■For the VHDL-AMS netlist language, each terminal identifier should match the identifier of the external net to which the terminal connects.

If your design does not comply with this guideline, the netlister attempts to declare an alias of the terminal, where the alias has the name of the terminal.

In some cases, it is not possible to use an alias, such as when only a part of a bus is connected to a terminal or when a bus is connected to multiple terminals. In situations like this, the netlister attempts to create a VHDL block and to resolve the connection by using block port maps. The netlister warns you when it creates a VHDL block because all cross-probing capabilities inside the block are lost.

Buses

To ensure that your design can proceed smoothly through the steps in the Virtuoso AMS environment flow, follow these guidelines dealing with buses.

■Use simple buses when you declare vector terminals or nets.

Avoiding the use of concatenated non-consecutive bits, ranges with increment values other than one, prefix repeat operators, and suffix repeat operators is especially important when declaring terminals. For example, you have a terminal on a schematic with the identifier<*2>term, connected to a 2-bit wide net. The netlister, however, writes the identifier as a single-bit port calledterm. Attempting to connect the single-bit port described in the netlist to the 2-bit wide net results in failure.

For nets, an identifier likenet1,net1 is written to the netlist as a concatenation, in this example, {net1,net1}. You can successfully simulate with this concatenation, but you lose the ability to cross-probe the net.

■Use a consistent range direction when declaring and using each bus. Choose either

MSB:LSB or LSB:MSB.

Using a bus or a subsection of a bus with a range direction different from the declared range direction for that bus forces the netlister to write the bus instance as a concatenation of bits. Because the concatenation does not match the original declaration, you lose the ability to cross-probe the net that includes the bus.

■Do not declare sparse buses.

Using sparse buses hinders or prevents cross-probing. For example, you declare a bus in the schematic as busname<15:0:2>, which is an 8-bit net. Because sparse buses are overdeclared, the netlister writes the bus to the netlist as busname[15:0], which is a 16-bit net. As a result, the connections have to be written as a concatenation of the eight odd-numbered bits of busname. This concatenation does not match the original