- •Contents
- •Preface
- •Related Documents
- •Typographic and Syntax Conventions
- •Creating HDL Modules for CDBA Cellviews
- •Creating HDL Data as You Save CDBA Cellviews
- •Creating HDL Data from Pre-existing CDBA Cellviews
- •Quick-Start Tutorial
- •The Circuit
- •AMS Designer Tools
- •Setting Up the Tutorial
- •Running from a Script
- •Running within the AMS Environment
- •Opening the Command Interpreter Window
- •Netlisting and Compiling
- •Elaborating and Simulating the Design
- •Summary
- •Setting Up the AMS Environment
- •Overview
- •The hdl.var File
- •The ams.env Files
- •AMS Designer Supports Design Management
- •Specifying the Text Editor to Use
- •Specifying Fonts for the Cadence Hierarchy Editor
- •Preparing to Use AMS Designer from the Hierarchy Editor
- •Netlisting
- •Netlisting Modes Supported by the AMS Netlister
- •Automatic Netlisting of a Cellview
- •Netlist Updating and Netlisting of Entire Designs
- •Netlisting from the UNIX Command Line
- •Library Netlisting
- •Netlisting of Cells in Response to Changes in CDF
- •Preparing Existing Analog Primitive Libraries for Netlisting
- •Specifying the Behavior of the Netlister and Compilers
- •Opening the AMS Options Windows
- •Setting Netlister Options from the Hierarchy Editor
- •Opening the CIW AMS Options Window
- •Setting Compiler Options
- •Viewing the AMS Netlister Log
- •Understanding the Output from the AMS Netlister
- •How Inherited Connections Are Netlisted
- •Inherited Signal Connections
- •Inherited Terminal Connections
- •Instance Values for Inherited Connections
- •Third-Party Tools and Other Cadence Tools
- •How Aliased Signals Are Netlisted
- •How m-factors (Multiplicity Factors) Are Netlisted
- •How Iterated Instances Are Netlisted
- •Passing Model Names as Parameters
- •Effect of the modelname, model, and modelName Parameters
- •Handling of the model* and componentName Parameters
- •Precedence of the model* and componentName Parameters
- •Specifying Parameters to be Excluded from Netlisting
- •Ignoring Parameters for Entire Libraries
- •Example: Specifying Parameters to Ignore
- •Ensuring that Floating Point Parameters Netlist Correctly
- •Working with Schematic Designs
- •Setting Schematic Rules Checker Options for AMS Designer
- •Creating Cellviews Using the AMS Environment
- •Preparing a Library
- •Creating the Symbol View
- •Using Blocks
- •Descend Edit
- •Inherited Connections
- •Global Signals in the Schematic Editor
- •Inherited Connections in a Hierarchy
- •How Net Expressions Evaluate
- •Net and Pin Properties
- •groundSensitivity and supplySensitivity Properties
- •Making Connect Modules Sensitive to Inherited Connection Values
- •Using External Text Designs
- •Overview of Steps for Using External Text Designs
- •Bringing Modules into a Cadence Library
- •Specifying the Working Library
- •Compiling into Libraries
- •Compiling into Temporary Libraries
- •Listing Compiled Modules
- •Using Text Blocks in Schematics
- •Using Modules Located in a Cadence Library
- •Preparing for Simulation
- •Using Analog Primitives
- •Using SPICE and Spectre Netlists and Subcircuits
- •Preparing to Use SPICE and Spectre Netlists and Subcircuits
- •Placing SPICE and Spectre Netlists and Subcircuits in a Schematic
- •Using Test Fixtures
- •Creating and Using a Textual Test Fixture
- •Creating a Textual Test Fixture
- •Using a Test Fixture
- •Example: Creating and Using a Test Fixture
- •Using Design Configurations
- •Ensuring HDL Design Unit Information Is Current
- •Preparing a Design for Simulation
- •Overview of AMS Design Prep
- •What AMS Design Prep Does to Prepare a Design for Simulation
- •When to Use AMS Design Prep
- •Specifying the Behavior of AMS Design Prep
- •Setting Options for Global Design Data
- •Specifying Global Signals
- •Specifying Design Variables
- •Specifying Model Files to Use During Elaboration
- •Running AMS Design Prep
- •The cds_globals Module
- •Global Signals
- •Design Variables
- •Setting Elaborator Options
- •Setting Simulator Options
- •Setting Waveform Selection Options
- •Creating Probes
- •Selecting Instances from the Virtuoso Schematic Editing Window
- •Selecting Buses
- •Selecting Instances from the Scope Navigator
- •Copying and Pasting Within Tables
- •Elaborating and Simulating
- •Viewing Messages
- •Plotting Waveforms After Simulation Ends
- •Starting the SimVision Waveform Viewer
- •Plotting Waveforms Selected on a Schematic (Direct Plot)
- •Using the amsdesigner Command
- •Examples
- •Producing Customized Netlists
- •Producing Customized Netlists
- •Identifying the Sections of a Netlist
- •Using ams.env Variables to Customize Netlists
- •Using Netlisting Procedures to Customize Netlists
- •Examples: Problems Addressed by Customized Netlists
- •Example: Adjusting Parameter Values to Account for Number of Fingers
- •Example: Using Symbols that Represent Verilog Test Code
- •Data Objects Supported for Netlisting
- •Netlister Object
- •Formatter Object
- •Cellview Object
- •Parameter Object
- •Instance Object
- •SKILL Functions Supported for Netlisting
- •Default Netlisting Procedures
- •Netlisting Helper Functions
- •Variables for ams.env Files
- •How AMS Designer Determines the Set of Variables
- •Why AMS Designer Uses ams.env Files, Not .cdsenv Files
- •List of ams.env Variables
- •Detailed Descriptions of ams.env Variables
- •aliasInstFormat
- •allowDeviantBuses
- •allowNameCollisions
- •allowSparseBuses
- •allowUndefParams
- •amsCompMode
- •amsDefinitionViews
- •amsEligibleViewTypes
- •amsExcludeParams
- •amsExpScalingFactor
- •amsLSB_MSB
- •amsMaxErrors
- •amsScalarInstances
- •amsVerbose
- •analogControlFile
- •bindCdsAliasLib
- •bindCdsAliasView
- •cdsGlobalsLib
- •cdsGlobalsView
- •checkAndNetlist
- •checkOnly
- •checktasks
- •compileAsAMS
- •compileExcludeLibs
- •compileMode
- •connectRulesCell
- •connectRulesCell2
- •connectRulesLib
- •connectRulesView
- •detailedDisciplineRes
- •discipline
- •excludeViewNames
- •hdlVarFile
- •headerText
- •ieee1364
- •ifdefLanguageExtensions
- •incdir
- •includeFiles
- •includeInstCdfParams
- •initFile
- •instClashFormat
- •iterInstExpFormat
- •language
- •lexpragma
- •logFileAction
- •logFileName
- •macro
- •maxErrors
- •messages
- •modifyParamScope
- •ncelabAccess
- •ncelabAnnoSimtime
- •ncelabArguments
- •ncelabCoverage
- •ncelabDelayMode
- •ncelabDelayType through ncelabMessages
- •ncelabMixEsc
- •ncelabModelFilePaths
- •ncelabNeverwarn through ncelabVipdelay
- •ncsimArguments
- •ncsimEpulseNoMsg through ncsimExtassertmsg
- •ncsimGUI
- •ncsimLoadvpi through ncsimStatus
- •ncsimTcl
- •ncsimUnbuffered through ncsimUseAddArgs
- •ncvhdlArguments
- •ncvlogArguments
- •ncvlogUseAddArgs
- •netClashFormat
- •netlistAfterCdfChange
- •netlistMode
- •netlistUDFAsMacro
- •neverwarn
- •noline
- •nomempack
- •nopragmawarn
- •nostdout
- •nowarn
- •paramDefVals
- •paramGlobalDefVal
- •pragma
- •processViewNames
- •prohibitCompile
- •runNcelab
- •runNcsim
- •scaddlglblopts
- •scaddltranopts
- •scale
- •scalem
- •scannotate
- •scapprox
- •scaudit
- •sccheckstmt
- •sccmin
- •sccompatible
- •scdebug
- •scdiagnose
- •scdigits
- •scerror
- •scerrpreset
- •scfastbreak
- •scgmin
- •scgmincheck
- •schomotopy
- •sciabstol
- •scic
- •scicstmt
- •scignshorts
- •scinfo
- •scinventory
- •sclimit
- •sclteratio
- •scmacromod
- •scmaxiters
- •scmaxnotes
- •scmaxrsd
- •scmaxstep
- •scmaxwarn
- •scmethod
- •scmodelevaltype
- •scmosvres
- •scnarrate
- •scnotation
- •scnote
- •scopptcheck
- •scpivabs
- •scpivotdc
- •scpivrel
- •scquantities
- •screadic
- •screadns
- •screlref
- •screltol
- •scrforce
- •scscale
- •scscalem
- •scscftimestamp
- •scscfusefileflag
- •scskipcount
- •scskipdc
- •scskipstart
- •scskipstop
- •scspeed
- •scstats
- •scstep
- •scstop
- •scstrobedelay
- •scstrobeperiod
- •sctemp
- •sctempeffects
- •sctitle
- •sctnom
- •sctopcheck
- •sctransave
- •scusemodeleval
- •scvabstol
- •scwarn
- •scwrite
- •simRunDirLoc
- •simVisScriptFile
- •status
- •templateFile
- •templateScript
- •timescale
- •update
- •use5xForVHDL
- •useDefparam
- •useNcelabNowarn
- •useNcelabSdfCmdFile
- •useNcsimNowarn
- •useNowarn
- •useScaddlglblopts
- •useScaddltranopts
- •useScic
- •useScreadic
- •useScreadns
- •useScwrite
- •useSimVisScriptFile
- •useProcessViewNamesOnly
- •verboseUpdate
- •vlogGroundSigs
- •vloglinedebug
- •vlogSupply0Sigs
- •vlogSupply1Sigs
- •wfDefaultDatabase
- •wfDefInstCSaveAll
- •wfDefInstCSaveLvl
- •wfDefInstSaveCurrents
- •wfDefInstSaveVoltages
- •wfDefInstVSaveAll
- •wfDefInstVSaveLvl
- •wfDefInstVSaveObjects
- •Updating Legacy SimInfo for Analog Primitives
- •The ams Fields
- •Special Handling of model, modelName, modelname, and componentName
- •Converting an Existing Analog Primitive Library
- •Designing for Virtuoso AMS Compliance
- •Terminals
- •Buses
- •Component Description Format
- •Parameters
- •Using Inherited Parameters
- •Using Cell Parameters
- •Parameterized Cells
- •VHDL-AMS Component Declarations
- •Properties
- •Properties to Avoid Completely
- •Avoid the portOrder Property Unless Required by Special Circumstances
- •Properties to Use Only in AMS Compatibility Mode
- •Properties That Have No Special Meaning in the AMS Environment
- •Properties Fully Supported by the AMS Environment
- •SKILL Functions
- •amsCheckCV
- •amsIsPresent
- •amsNetlist
- •amsProcessCellViews
- •amsUIOptionsForm
- •amsUIRunNetlisterForm
- •ddsCvtAMSTranslateCell
- •ddsCvtAMSTranslateLib
- •ddsCvtToolBoxAMS
- •vmsUpdateCellViews
- •Customization Variables
- •schHdlNotCreateDB
- •schHdlUseVamsForVerilog
- •vmsAnalysisType
- •vmsCreateMissingMasters
- •vmsNcvlogExecutable
- •vmsPortProcessing
- •vmsRunningInUI
- •vmsTemplateScript
- •vmsVerboseMsgLevel
- •Compiling Cadence-Provided Libraries
- •Purpose of the amsLibCompile Tool
- •Running the amsLibCompile Tool Manually
- •Example
Virtuoso AMS Environment User Guide
12
Using the amsdesigner Command
The amsdesigner command allows you to run AMS Designer from the command line or from a script. The command includes options for netlisting, compiling, elaborating, and simulating.
amsdesigner_command ::=
|
amsdesigner [-help | -version] |
| |
amsdesigner -lib libName -cell cellName -view viewName |
|
action_option {action_option} |
|
[-log logFileName] |
|
[-cdslib filePath] |
|
[-cdsglobals overwriteEdits | retainEdits] |
action_option ::= |
|
|
-netlist incremental | all | none |
| |
-compile whenNetlist | all | none |
| |
-elaborate |
| |
-simulate |
The following table describes the amsdesigner command options and values.
amsdesigner Option and |
Effect |
|
Value |
|
|
|
|
|
-LIb libName |
Specifies the library containing the configuration that you |
|
|
want to process. |
|
-CEll cellName |
Specifies the cell containing the configuration that you want |
|
|
to process. |
|
-VIew viewName |
Specifies the cellview name of the configuration that you |
|
|
want to process. The amsdesigner command opens this |
|
|
configuration in read-only mode. |
April 2004 |
295 |
Product Version 5.3 |
Virtuoso AMS Environment User Guide
Using the amsdesigner Command
amsdesigner Option and |
Effect |
Value |
|
|
|
-LOg logFileName |
Tells the amsdesigner tool to write messages to |
|
logFileName. Default: ./amsdesigner.log |
|
■ If logFileName is an absolute path, the log file is |
|
written to logFileName. |
|
■ If logFileName is a relative path, logFileName is |
|
placed in a location that is relative to the current |
|
directory. |
-CDSLib filePath |
Specifies a cdslib file to load. Default:./cds.lib |
-CDSGlobals |
You can omit the -CDSGlobals option if the cds_globals |
|
module has not been edited by hand. If the cds_globals |
|
module has been edited by hand, you must use the |
|
-CDSGlobals option and you must specify a value for the |
|
option. |
overwriteEdits |
Tells the amsdesigner tool to regenerate and overwrite the |
|
cds_globals module as necessary, even if the module |
|
has been edited by hand. |
retainEdits |
Tells the amsdesigner tool not to overwrite a hand-edited |
|
cds_globals module. However, the retainEdits value |
|
allows the tool to overwrite the cds_globals module if the |
|
module has not been edited by hand. |
-Help |
Returns a brief description of the amsdesigner command |
|
and its options. |
-VERSion |
Returns version information, including the versions of the |
|
amsdesigner, hierarchy editor, amsdirect, and ncvlog tools |
|
and the versions of input and output files used by the |
|
hierarchy editor. |
-Netlist |
|
incremental |
Tells the amsdesigner tool to produce Verilog-AMS netlists |
|
for only new or revised cellviews. |
all |
Tells the amsdesigner tool to netlist all cellviews in the |
|
configuration, whether they have changed since the |
|
previous netlisting or not. |
none |
Turns off netlisting for all cellviews. This is the default value |
|
when the -Netlist option is not specified. |
April 2004 |
296 |
Product Version 5.3 |
Virtuoso AMS Environment User Guide
Using the amsdesigner Command
amsdesigner Option and |
Effect |
Value |
|
|
|
-COmpile |
|
whenNetlist |
Tells the amsdesigner tool to compile only cellviews |
|
netlisted in this run. |
all |
Tells the amsdesigner tool to compile all cellviews in the |
|
configuration, whether netlisted in this run or not. |
none |
Turns off compilation for all cellviews. This is the default |
|
value when the -COmpile option is not specified. |
-Elaborate |
Tells the amsdesigner tool to elaborate the design. |
-Simulate |
Tells the amsdesigner tool to simulate the design. |
|
|
The amsdesigner command is intended for rerunning designs that have been previously simulated with the AMS environment. The amsdesigner command uses setup information that cannot be entered as options on the command line. Before you can run the amsdesigner command, you must provide that setup information by using the windows in the AMS environment. To ensure that the setup information is usable, the run directory and input files used during the AMS environment simulation must then remain unchanged for runs of the amsdesigner command.
Note that it is possible to specify combinations of action options for the amsdesigner command that do not produce usable results. For example, if you specify that netlists are to be generated but not compiled, elaboration fails because the expected new netlists are not found.
Examples
The following command netlists, compiles, elaborates, and simulates the whole design.
amsdesigner -lib mylib -cell top -view config -netlist all -compile all -elaborate -simulate
The following command netlists the cellviews in the design that have been revised, then compiles just those newly netlisted cellviews. The design is neither elaborated nor simulated.
amsdesigner -lib amsLib -cell top -view config -netlist incremental -compile whenNetlist
The following command returns the versions of the tools and files used by theamsdesigner command and then exits. If you need to communicate with Cadence, you might use a command like this to obtain useful background information.
April 2004 |
297 |
Product Version 5.3 |
Virtuoso AMS Environment User Guide
Using the amsdesigner Command
amsdesigner -version
The returned information includes information about the tools and files used by the amsdesigner command.
@(#)$CDS: amsdesigner 5.0.0 07/09/2003 22:25 (cds12107) $
Tool: |
cdsHierEditor |
05.01.000-b005 |
|
Input: |
expand.cfg |
04.04.003 |
|
Input: |
expand.cfg |
05.00.000 |
|
Input: |
pc.db |
01.00 |
|
Output: |
expand.cfg |
05.00.000 |
|
Output: |
Verilog |
1364-1995 |
|
Output: |
VHDL |
1076-1993 |
@(#)$CDS: amsdirect version 5.0.0 07/10/2003 15:11 (cds12107) $ ncvlog: v04.00.(s019)
April 2004 |
298 |
Product Version 5.3 |