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Национальный исследовательский университет «МИЭТ»

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	Accellera
Analog and Mixed-signal Extensions to Verilog HDL	Version 2.3.1, June 1, 2009

9. System tasks and functions

9.1 Overview

Verilog-AMS HDL is a superset of IEEE std 1364-2005 Verilog HDL and hence all the system tasks in IEEE std 1364-2005 Verilog HDL are supported. Verilog-AMS adds several system tasks and system functions. These are described in this clause. In addition, Verilog AMS HDL extends the behavior of several Verilog systems tasks and functions including allowing some of them to be used in an analog context.

The system task and functions support by Verilog-AMS HDL are categorized in 9.2. A subclause is devoted to each category from 9.4 until the end of this clause.

The behavior of a system task or function which is allowed in an analog context will be described in the context of the analog simulation cycle (9.2) if required in the relevant section for that system task or function.

9.2 Categories of system tasks and functions

This subclause describes system tasks and functions that are considered part of the Verilog-AMS HDL. It also states whether a particular system task or function is supported in the digital context and if it is supported in the analog context. The system tasks and functions are divided into sixteen categories. Each category has a table describing the support level in Verilog-AMS HDL for the system task or functions in that category.

Table 9-1—Display system tasks

Task name	Supported in digital context	Supported in analog context

$display	Yes	Yes

$displayb, $displayh, $displayo	Yes	No

$strobe	Yes	Yes

$strobeb, $strobeh, $strobeo	Yes	No

$write	Yes	Yes

$writeb, $writeh, $writeo	Yes	No

$monitor	Yes	No

$monitorb, $monitorh, $monitoro	Yes	Yes

$monitoron, $monitoroff	Yes	No

$debug	No	Yes

Table 9-2—File input-output system tasks and functions

Task/function name(s)	Supported in digital context	Supported in analog context

$fclose, $fopen	Yes	Yes

$fdisplay	Yes	Yes

$fdisplayb, $fdisplayh, $fdisplayo	Yes	No

193	Copyright © 2009 Accellera Organization, Inc. All rights reserved.

Accellera
Version 2.3.1, June 1, 2009	VERILOG-AMS

Table 9-2—File input-output system tasks and functions (continued)

Task/function name(s)	Supported in digital context	Supported in analog context

$fwrite	Yes	Yes

$fwriteb, $fwriteh, $fwriteo	Yes	No

$fstrobe	Yes	Yes

$fstrobeb, $fstrobeh, $fstrobeo	Yes	No

$fmonitor	Yes	Yes

$fmonitorb, $fmonitorh, $fmonitoro	Yes	No

$fgetc, $ungetc	Yes	No

$fgets	Yes	Yes

$fscanf	Yes	Yes

$swrite, $sformat, $sscanf	Yes	Yes

$swriteb, $swriteh, $swriteo	Yes	No

$fread	Yes	No

$rewind, $fseek, $ftell	Yes	Yes

$fflush	Yes	Yes

$ferror	Yes	Yes

$feof	Yes	Yes

$readmemb, $readmemh	Yes	No

$sdf_annotate	Yes	No

$fdebug	No	Yes

Table 9-3—Timescale system tasks

Task/Function Name(s)	Supported in Digital Context	Supported in Analog Context

$printtimescale	Yes	No

$timeformat	Yes	No

Table 9-4—Simulation control system tasks

Task name	Supported in digital context	Supported in analog context

$finish	Yes	Yes

$stop	Yes	Yes

$fatal	No	Yes

194

	Accellera
Analog and Mixed-signal Extensions to Verilog HDL	Version 2.3.1, June 1, 2009

Table 9-4—Simulation control system tasks (continued)

Task name	Supported in digital context	Supported in analog context

$warning	No	Yes

$error	No	Yes

$info	No	Yes

Table 9-5—PLA modeling system tasks

Task name	Supported in digital context	Supported in analog context

$async$and$array	Yes	No

$async$nand$array	Yes	No

$async$or$array	Yes	No

$async$nor$array	Yes	No

$sync$and$array	Yes	No

$sync$nand$array	Yes	No

$sync$or$array	Yes	No

$sync$nor$array	Yes	No

$async$and$plane	Yes	No

$async$nand$plane	Yes	No

$async$or$plane	Yes	No

$async$nor$plane	Yes	No

$sync$and$plane	Yes	No

$sync$nand$plane	Yes	No

$sync$or$plane	Yes	No

$sync$nor$plane	Yes	No

Table 9-6—Stochastic analysis system tasks

Task name	Supported in digital context	Supported in analog context

$q_initialize	Yes	No

$q_remove	Yes	No

$q_exam	Yes	No

$q_add	Yes	No

$q_full	Yes	No

195	Copyright © 2009 Accellera Organization, Inc. All rights reserved.

Accellera
Version 2.3.1, June 1, 2009	VERILOG-AMS

Table 9-7—Simulation time system functions

Function name	Supported in digital context	Supported in analog context

$realtime	Yes	No

$time	Yes	No

$stime	Yes	No

$abstime	Yes	Yes

Table 9-8—Conversion system functions

Function name	Supported in digital context	Supported in analog context

$bitstoreal	Yes	Yes

$itor	Yes	No

$signed	Yes	No

$realtobits	Yes	Yes

$rtoi	Yes	No

$unsigned	Yes	No

Table 9-9—Command line input system functions

Function name	Supported in digital context	Supported in analog context

$test$plusargs	Yes	Yes

$value$plusargs	Yes	Yes

Table 9-10—Probabilistic distribution system functions

Function name	Supported in digital context	Supported in analog context

$dist_chi_square	Yes	Yes

$dist_exponential	Yes	Yes

$dist_poisson	Yes	Yes

$dist_uniform	Yes	Yes

$dist_erlang	Yes	Yes

$dist_normal	Yes	Yes

196

	Accellera
Analog and Mixed-signal Extensions to Verilog HDL	Version 2.3.1, June 1, 2009

Table 9-10—Probabilistic distribution system functions (continued)

Function name	Supported in digital context	Supported in analog context

$dist_t	Yes	Yes

$random	Yes	Yes

$arandom	Yes	Yes

$rdist_chi_square	Yes	Yes

$rdist_exponential	Yes	Yes

$rdist_poisson	Yes	Yes

$rdist_uniform	Yes	Yes

$rdist_erlang	Yes	Yes

$rdist_normal	Yes	Yes

$rdist_t	Yes	Yes

Table 9-11—Math system functions

Function name	Supported in digital context	Supported in analog context

$clog2	Yes	Yes

$ln	Yes	Yes

$log10	Yes	Yes

$exp	Yes	Yes

$sqrt	Yes	Yes

$pow	Yes	Yes

$floor	Yes	Yes

$ceil	Yes	Yes

$sin	Yes	Yes

$cos	Yes	Yes

$tan	Yes	Yes

$asin	Yes	Yes

$acos	Yes	Yes

$atan	Yes	Yes

$atan2	Yes	Yes

$hypot	Yes	Yes

$sinh	Yes	Yes

$cosh	Yes	Yes

$tanh	Yes	Yes

197	Copyright © 2009 Accellera Organization, Inc. All rights reserved.

Accellera
Version 2.3.1, June 1, 2009	VERILOG-AMS

Table 9-11—Math system functions (continued)

Function name	Supported in digital context	Supported in analog context

$asinh	Yes	Yes

$acosh	Yes	Yes

$atanh	Yes	Yes

Table 9-12—Analog kernel parameter system functions

Function Name	Supported in digital context	Supported in analog context

$temperature	Yes	Yes

$vt	Yes	Yes

$simparam	Yes	Yes

$simparam$str	Yes	Yes

Table 9-13—Dynamic simulation probe system function

Function Name	Supported in digital context	Supported in analog context

$simprobe	No	Yes

Table 9-14—Analog kernel control system tasks and functions

Task/function name	Supported in digital context	Supported in analog context

$discontinuity	No	Yes

$limit	No	Yes

$bound_step	No	Yes

Table 9-15—Hierarchical parameter system functions

Function name	Supported in digital context	Supported in analog context

$mfactor	Yes	Yes

$xposition	Yes	Yes

$yposition	Yes	Yes

$angle	Yes	Yes

198

	Accellera
Analog and Mixed-signal Extensions to Verilog HDL	Version 2.3.1, June 1, 2009

Table 9-15—Hierarchical parameter system functions (continued)

Function name	Supported in digital context	Supported in analog context

$hflip	Yes	Yes

$vflip	Yes	Yes

Table 9-16—Explicit binding detection system functions

Function name	Supported in digital context	Supported in analog context

$param_given	No	Yes

$port_connected	No	Yes

Table 9-17—Table based interpolation and lookup system function

Function name	Supported in digital context	Supported in analog context

$table_model	Yes	Yes

Table 9-18—Connectmodule driver access system functions and operator

Function/operator name	Supported in digital context	Supported in analog context
Function/operator name	of connectmodule	of connectmodule
	of connectmodule	of connectmodule

$driver_count	Yes	No

$driver_state	Yes	No

$driver_strength	Yes	No

@(driver_update)	Yes	No

Table 9-19—Supplementary connectmodule driver access system functions

Task/Function Name(s)	Supported in Digital Context	Supported in Analog Context
Task/Function Name(s)	of Connectmodule	of Connectmodule
	of Connectmodule	of Connectmodule

$driver_delay	Yes	No

$driver_next_state	Yes	No

$driver_next_strength	Yes	No

$driver_type	Yes	No

199	Copyright © 2009 Accellera Organization, Inc. All rights reserved.

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