In this case, a digital event, such as posedge or negedge, appears in an @() statement in the analog context.

When it is determined the event has occurred in the digital domain, the statements under the event control shall be executed in the analog domain at the time corresponding to a real promotion of the digital time (e.g.,

27ns to 27.0e-9).

7.3.6.3 Analog primary appearing in a digital expression

In this case, an analog primary (variable, potential, or flow) whose value is calculated in the continuous domain appears in a expression which is in the digital context; thus the analog primary is evaluated in the digital domain.

The expression shall be evaluated using the analog value calculated for the time corresponding to a real promotion of the digital time at which the expression is evaluated.

If the current time in the continuous and discrete kernels differ, interpolation is used to determine the value to be used in the discrete context for the continuous variable unless the value of the continuous variable was last assigned in an analog event statement. In this case, the value used in the digital context is exactly the same as the last value assigned to the continuous variable.

7.3.6.4 Analog variables appearing in continuous assigns

Analog variables that are only assigned values within analog event statements can be used in the expressions that drive continous assigns, both when the target of the continuous assign is a wreal or a traditional Verilog wire type (wire, trireg, wor, wand, etc.).

7.3.6.5 Digital primary appearing in an analog expression

In this case, a digital primary (reg, wire, integer, etc.) whose value is calculated in the discrete domain appears in an expression which is in the analog context; thus the analog primary is evaluated in the continuous domain.

The expression shall be evaluated using the digital value calculated for the greatest digital time tick which is less than or equal to the analog time when the expression is evaluated.

7.3.7 Function calls

Digital functions cannot be called from within the analog context. Analog functions cannot be called from within the digital context.

7.4 Discipline resolution

In general a mixed signal is a collection of nets, some with discrete discipline(s) and some with continuous discipline(s). Additionally, some of the nets can have undeclared discipline(s). Discipline resolution assigns disciplines to those nets whose discipline is undeclared. This is done to control auto-insertion of connect modules, according to the rules embodied in connect statements.

The assignments are based on: discipline declarations, `default_discipline directives (see 3.8), and the hierarchical connectivity of the design. Once all net segments of every mixed signal has been resolved, insertion of connect modules shall be performed.

7.4.1 Compatible discipline resolution

One factor which influences the resolved discipline of a net whose discipline is undeclared is the disciplines of nets to which it is connected via ports; i.e., if multiple compatible disciplines are connected to the same net via multiple ports only one discipline can be assigned to that net. This is controlled by the resolveto form of the connect statement; the syntax of this form is described in 7.7.2.

If disciplines at the lower connections of ports (where the undeclared net is an upper connection) are among the disciplines in discipline_list, the result_discipline is the discipline which is assigned to the undeclared net. If all the nets are of the same discipline, no rule is needed; that discipline becomes the resolved discipline of the net.

In the example shown in Figure 7-2, NetA and NetB are undeclared interconnects. NetB has cmos3 and cmos4 at the lower connection ports, while it is an upper connection.

cmos4

cmos2

module blk (out);

module blk (out);

connect cmos3 cmos4 resolveto cmos3; connect cmos1 cmos2 cmos3 resolveto cmos1;

Figure 7-2: Compatible discipline resolution

The first connect statement resolves NetB to be assigned the discipline cmos3.

NetA has cmos1, cmos2 and the resulting cmos3 from module twoblks at the lower connection ports; based on the second connect statement, it resolves to be assigned the discipline cmos1.

7.4.2 Connection of discrete-time disciplines

Ports of discrete-time disciplines (ports where digital signals appear at both upper (vpiHiConn) and lower (vpiLoConn) connections) shall obey the rules imposed by IEEE std 1364-2005 Verilog HDL on such connections.

In addition, the real-value nets shall obey the rules imposed by 3.7.

7.4.3 Connection of continuous-time disciplines

Ports of continuous-time disciplines (ports where analog signals appear at both upper (vpiHiConn) and lower (vpiLoConn) connections) shall obey the rules imposed in 3.11. It shall be an error to connect incompatible continuous disciplines together.