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Accellera

Analog and Mixed-signal Extensions to Verilog HDL

Version 2.3.1, June 1, 2009

V(p,n) <+ 0;

is equivalent to

if (closed) V(p,n) <+ 0;

else

I(p,n) <+ 0;

Example 2:

The value retention rules specify that the example below will result in an assignment of 7.0 to the potential source for the unnamed branch between ports p and n.

module value_ret(p, n); inout p, n; electrical p, n; analog begin

V(p,n) <+ 1.0; // no previously-retained value, 1 is retained I(p,n) <+ 2.0; // potential discarded; flow of 2 retained V(p,n) <+ 3.0; // flow discarded; potential of 3 retained V(p,n) <+ 4.0; // 4 added to previously-retained 3

end endmodule

Example 3:

The following module defines a current-controlled current source. Because the branch flow I(ps,ns) appears in an expression on the right-hand side, 5.4.2.1 states that this unnamed branch is a probe and its potential is zero (0).

module cccs (p, n, ps, ns); inout p, n, ps, ns; electrical p, n, ps, ns; parameter real A = 1.0; analog begin

I(p,n) <+ A * I(ps,ns); end

endmodule

The value retention rules are used to model switches, as described in 5.6.5.

5.6.2 Examples

The following examples demonstrate how to formulate models and the correspondence between the behavioral description and the equivalent probe/source model.

5.6.2.1 The four controlled sources

The following example is used with each of the four behavioral statements listed below. Each statement creates a unique controlled source when inserted into this example.

module control_source (p, n, ps, ns); inout p, n, ps, ns;

electrical p, n, ps, ns; parameter A=1;

branch (ps,ns) in;

99

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