—A paramset output variable’s value may be computed from values of any output parameters of the module by using the special syntax

.module_output_variable_identifier

The following example declares an output variable ft for instances of the paramset smnpn.The module is assumed to have output variables named gm, cpi, and cmu. If the module npn had an output variable named ft, the paramset’s output variable would replace it.

paramset smnpn npn; // small npn paramset (*desc="cut-off frequency"*) real ft;

.is=2.0e-17; .bf=120.0; .br=10; rb=145; .rc=75; .re=12;

.cje=2.0e-14; .vje=0.9; .mje=0.4;

.cjc=3.0e-14; .vjc=0.6; .mjc=0.3; .xcjc=0.2; ft = .gm/(‘M_TWO_PI*(.cpi + .cmu));

endparamset

6.5 Ports

Ports provide a means of interconnecting instances of modules. For example, if a module A instantiates module B, the ports of module B are associated with either the ports or the internal nets of module A.

6.5.1 Port definition

The syntax for a port association is shown in Syntax 6-5.

Syntax 6-5—Syntax for port

The port expression in the port definition can be one of the following:

—a simple net identifier

—a scalar member of a vector net or port declared within the module

—a sub-range of a vector net or port declared within the module

—a vector net formed as a result of the concatenation operator

The port expression is optional because ports can be defined which do not connect to anything internal to the module.

6.5.2 Port declarations

The type and direction of each port listed in the module definition’s list of ports are declared in the body of the module.

6.5.2.1 Port type

The type of a port is declared by giving its discipline, as shown in Syntax 6-6. If the type of a port is not declared, the port can only be used in a structural description. (It can be passed to instances of modules, but cannot be accessed in a behavioral description.)

Syntax 6-6—Syntax for port type declarations

6.5.2.2 Port direction

Each port listed in the list of ports for the module definition shall be declared in the body of the module as an input, output, or inout (bidirectional). This is in addition to any other declaration for a particular port—for example, a net_discipline, reg, or wire. The syntax for port declarations is shown in Syntax 6-7.

inout [ discipline_identifier ] [ net_type | wreal ] [ signed ] [ range ] list_of_port_identifiers

input_declaration ::=

input [ discipline_identifier ] [ net_type | wreal ] [ signed ] [ range ] list_of_port_identifiers

output_declaration ::=

output [ discipline_identifier ] [ net_type | wreal ] [ signed ] [ range ] list_of_port_identifiers | output [ discipline_identifier ] reg [ signed ] [ range ] list_of_variable_port_identifiers

| output output_variable_type list_of_variable_port_identifiers

Syntax 6-7—Syntax for port direction declarations

A port can be declared in both a port type declaration and a port direction declaration. If a port is declared as a vector, the range specification between the two declarations of a port shall be identical.

Implementations can limit the maximum number of ports in a module definition, but this shall be a minimum of 256 ports per implementation.