2)Digital drivers of mixed signals are segregated from receivers so the digital drivers contribute to the analog state of the signal and the analog state determines the value seen by the receivers.

3)A connection shall be selected for a port only if one of the connections to the port is digital and the other is analog. In this case, the port shall match one (and only one) connect statement. The module named in the connect statement is the one which shall be selected for the port.

Once connect modules have been selected, they are inserted according to the connect_mode parameter in the pertinent connect statements. These rules apply to connect module insertion:

1)The connect mode of a port for which a connect module has been selected shall be determined by the value of the connect_mode parameter of the connect statement which was used to select the connect module.

2)The connect module for a port shall be instantiated in the context of the ports upper connection.

3)All ports connecting to the same signal (upper connection), sharing the same connect module, and having merged parameter shall share a single instance of the selected connect module.

4)All other ports shall have an instance of the selected connect module, i.e., one connect module instance per port.

7.8.5 Instance names for auto-inserted instances

Parameters of auto-inserted connect instances can be set on an instance-by-instance basis with the use of the defparam statement. This requires predictable instance names for the auto-inserted modules.

The following naming scheme is employed to unambiguously distinguish the connector modules for the case of auto-inserted instances.

1)merged

In the merged case, one or more ports have a given discipline at their bottom connection, call it BottomDiscipline, and a common signal, call it SigName, of another discipline at their top connection. A single connect module, call it ModuleName, is placed between the top signal and the bottom signals. In this case, the instance name of the connect module is derived from the signal name, module name, and the bottom discipline:

SigName__ModuleName__BottomDiscipline

2)split

In the split case, one or more ports have a given discipline at their bottom connection and a common signal of another discipline, call it TopDiscipline, at their top connection. One module instance is instantiated for each such port. In this case, the instance name of the connect module is

SigName__InstName__PortName

where InstName and PortName are the local instance name of the port and its instance respectively.

NOTE—The __ between the elements of these generated instance names is a double underscore.

7.8.5.1 Port names for Verilog built-in primitives

In the cases of instances of modules and instances of UDPs, port names are well defined. In these cases the port name is the name of the signal at the lower connection of the port. In the case of built-in digital primitives, however, IEEE std 1364-2005 Verilog HDL does not define port names. In order to support the unique naming of auto inserted connect modules and the ability to override the parameters of those connect modules, built-in digital primitives ports will be provided with predictable names. These names are only for the

purpose of naming the connect modules and do not define actual port names. These port names may not be used to instantiate or to do access of these primitives.

The following naming conventions shall be used when generating connect module instance names that are connected to built-in digital primitives.

1)For N-input gates (and, nand, nor, or, xnor, xor) the output will be named out, and the inputs reading from left to right will be in1, in2, in3, and so forth.

2)For N-output gates (buf, not) The input will be named in, and the outputs reading from left to right will be named out1, out2, out3, and so forth.

3)For 3 port MOS switches (nmos, pmos, rnmos, rpmos) the ports reading from left to right will be named source, drain, gate.

4)For 4 port MOS switches (cmos, rcmos) the ports reading from left to right will be named source, drain, ngate, pgate.

5)For bidirectional pass switches (tran, tranif1, tranif0, rtran, rtranif1, rtranif) the ports reading from left to right will be named source, drain, gate.

6)For single port primitives (pullup, pulldown) the port will be named out.

7.9Driver-receiver segregation

If the hierarchical segments of a signal are all digital or all analog, the signal is not a mixed signal and the internal representation of the signal does not differ from that of a purely digital or an analog signal.

If the signal has both analog and digital segments in its hierarchy, it is a mixed signal. In this case, the appropriate conversion elements are inserted, either manually or automatically, based on the following rules.

—All the analog segments of a mixed signal are representations of a single analog node.

—Each of the non-contiguous digital segments of a signal shall be represented internally as a separate digital signal, with its own state.

—Each non-contiguous digital segment shall be segregated into the collection of drivers of the segment and the collection of receivers of the segment.

In the digital domain, signals can have drivers and receivers. A driver makes a contribution to the state of the signal. A receiver accesses, or reads, the state of the signal. In a pure digital net, i.e., one without an analog segment, the simulation kernel resolves the values of the drivers of a signal and it propagates the new value to the receivers by means of an event when there is a change in state.

In the case of a mixed net, i.e., one with digital segments and an analog segment, it can be useful to propagate the change to the analog simulation kernel, which can then detect a threshold crossing, and then propagate the change in state back to the digital kernel. This, among other things, allows the simulation to account for rise and fall times caused by analog parasitics.

Within digital segments of a mixed-signal net, drivers and receivers of ordinary modules shall be segregated, so transitions are not propagated directly from drivers to receivers, but propagate through the analog domain instead. In this case, the drivers and receivers of connect modules shall be oppositely segregated; i.e., the connect module drivers shall be grouped with the ordinary module receivers and the ordinary module drivers shall be grouped with the connect module receivers.

Thus, digital transitions are propagated from drivers to receivers by way of analog (through using connect module instances). Figure 7-11 shows driver-receiver segregation in modules having bidirectional and unidirectional ports, respectively.

Figure 7-11: Driver-receiver segregation in modules with bidirectional ports