E.4.1 Unsupported primitives

Verilog-AMS HDL does not support the concept of passing an instance name as a parameter. As such, the following primitives are not supported: ccvs, cccs, and mutual inductors; however, these primitives can be instantiated inside a SPICE subcircuit that itself is instantiated in Verilog-AMS.

E.4.2 Discipline of primitives

To afford the ability to use analog primitive in any design, including mixed disciplines, the default discipline override is provided. The discipline of analog primitives will be resolved based on instance specific attributes, the disciplines of other instances on the same net, or default to electrical if it cannot be determined.

The precedence for the discipline of analog primitives is as follows:

1)A port_discipline attribute on the analog primitive;

2)The resolution of the discipline;

3)The default analog primitive of electrical.

E.4.2.1 Setting the discipline of analog primitives

A new optional attribute shall be provided called port_discipline, which shall have as a value the desired discipline for the port of the analog primitive. It shall only apply to either the analog primitive itself or the port to which it is attached. The value shall be of type string and the value must be a valid discipline of domain continuous. This attribute shall only apply to analog primitives or the ports of analog primitives; for other modules as well as the ports of all other modules it shall be ignored.

The following provides an example of this attribute applied to an analog primitive.

(* port_discipline="electrical" *) resistor #(.r(1k)) r1 (node1, node2); // not needed as default

(* port_discipline="rotational" *) resistor #(.r(1k)) r2 (node1, node2);

The following provides an example of this attribute applied to the ports of an analog primitive.

resistor #(.r(1k)) r3

((* port_discipline="rotational" *) node1, (* port_discipline="rotational" *) node2);

The use of these attributes can be combined to change the basic discipline of all ports for the analog primitive, but overriding the discipline for specific ports. The following provides an example of this use

(* port_discipline="electrical" *) vcvs #(.gain(1.45e-3)) motor1 (n1, gnd_e,

(* port_discipline="rotational_omega" *) shaft1, (* port_discipline="rotational_omega" *) gnd_rot);

The above model uses a voltage-controlled voltage source to model a motor as a converter from electrical potential to rotational velocity.

Attributes are described in 2.9 of this document.

E.4.2.2 Resolving the disciplines of analog primitives