scope. All unnamed generate blocks will be given the name "genblk<n>" where <n> is the number assigned to its enclosing generate construct. If such a name would conflict with an explicitly declared name, then leading zeroes are added in front of the number until the name does not conflict.

Each generate construct is assigned its number as described in the previous paragraph even if it does not contain any unnamed generate bocks.

Example:

module top ();

parameter genblk2 = 0; genvar i;

//The following generate block is implicitly named genblk1 if (genblk2) electrical a; // top.genblk1.a

else electrical b; // top.genblk1.b

//The following generate block is implicitly named genblk02

//as genblk2 is already a declared identifier if (genblk2) electrical a; // top.genblk02.a else electrical b; // top.genblk02.b

//The following generate block would have been named genblk3

//but is explicitly named g1

for (i = 0; i < 1; i = i + 1) begin : g1 // block name

//The following generate block is implicitly named genblk1

//as the first nested scope inside of g1

if (1) electrical a; // top.g1[0].genblk1.a end

//The following generate block is implicitly named genblk4 since

//it belongs to the fourth generate construct in scope "top".

//The previous generate block would have been named genblk3

//if it had not been explicitly named g1

for (i = 0; i < 1; i = i + 1)

//The following generate block is implicitly named genblk1

//as the first nested generate block in genblk4

if (1) electrical a; // top.genblk4[0].genblk1.a

// The following generate block is implicitly named genblk5 if (1) electrical a; // top.genblk5.a

endmodule

6.7 Hierarchical names

Every identifier in Verilog-AMS HDL has a unique hierarchical path name. The hierarchy of modules and the definition of items such as named blocks within the modules define these names. The hierarchy of names can be viewed as a tree structure, where each module instance or a named begin-end block defines a new hierarchical level, or as a scope (of a particular branch of the tree).

At the top of the name hierarchy are the names of modules where no instances have been created. This is the root of the hierarchy. Inside any module, each module instance and named begin-end block define a new branch of the hierarchy. Named blocks within named blocks also create new branches.

Each net in the hierarchical name tree is treated as a separate scope with respect to identifiers. A particular identifier can be declared only once in any scope.

Any named object can be referenced uniquely in its full form by concatenating the names of the module instance or named blocks that contain it. The period character (.) is used to separate names in the hierarchy. The complete path name to any object starts at a top-level module. This path name can be used from any level in the description. The first name in a path name can also be the top of a hierarchy which starts at the level where the path is being used.

Examples:

module samplehold (in, cntrl, out); input in, cntrl;

output out;

electrical in, cntrl, out; electrical store, sample; parameter real vthresh = 0.0; parameter real cap = 10e-9; amp op1 (in, sample, sample); amp op2 (store, out, out);

analog begin

I(store) <+ cap * ddt(V(store)); if (V(cntrl) > vthresh)

V(store, sample) <+ 0; else

I(store, sample) <+ 0;

end endmodule

module amp(inp, inm, out); input inp, inm;

output out;

electrical inp, inm, out; parameter real gain=1e5;

analog begin

V(out) <+ gain*V(inp,inm); end

endmodule

Figure 6-2 illustrates the hierarchy implicit in the example code.

samplehold

Figure 6-2: Hierarchy in a model

Figure 6-3 is a list of the hierarchical forms of the names of all the objects defined in the example code.