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Accellera

Analog and Mixed-signal Extensions to Verilog HDL

Version 2.3.1, June 1, 2009

endmodule

can bridge a mixed output port whose upper connection is compatible with discipline ddiscrete and whose lower connection is compatible with electrical, or a mixed input port whose upper connection is compatible with discipline electrical and whose lower connection is compatible with ddiscrete.

Example 3:

connectmodule bidir (out, in); inout out;

inout in; ddiscrete out; electrical in;

// insert connect module behavioral here endmodule

can bridge any mixed port whose one connection is compatible with discipline ddiscrete and whose connection is compatible with electrical.

7.7 Connect specification statements

Any number of connect modules can be defined. The designer can choose and specialize those in the design via the connect specification statements. The connect specification statements allow the designer to define:

specification of which connect module is used, including parameterization, for bridging given discrete and continuous disciplines

overrides for the connect module default disciplines and port directions

resolution of incompatible disciplines

The syntax for connect specifications is shown in Syntax 7-5.

connectrules_declaration ::=

// from A.1.8

connectrules connectrules_identifier ;

 

{ connectrules_item }

 

endconnectrules

 

connectrules_item ::=

 

connect_insertion

 

| connect_resolution

 

Syntax 7-5—Syntax for connect specification statements

The two forms of the connect specification statements and their syntaxes are detailed in the following subclauses.

7.7.1 Connect module auto-insertion statement

The connect module insertion statement declares which connect modules are automatically inserted when mixed nets of the appropriate types are encountered, as shown in Syntax 7-6.

This specifies the connect module connect_module_identifier is used to determine the mixed nets of the type used in the declaration of the connect module.

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