7.4.4 Resolution of mixed signals

Once discipline declarations and the `default_discipline compiler directive have been applied, if any mixed-signal nets are still undeclared additional resolution is needed. This section provides an additional method for discipline resolution of remaining undeclared nets (to control the auto-insertion of connect modules).

There are two modes for this method of resolution, basic (the default) and detail, which determine how known disciplines are used to resolve these undeclared nets. For the entire design, undeclared nets shall be resolved at each level of the hierarchy where continuous (analog) has precedence over discrete (digital). The selection of these discipline resolution modes shall be vendor-specific.

More than one conflicting discipline declaration from the same context (in or out of context) for the same hierarchical segment of a signal is an error. In this case, conflicting simply means an attempt to declare more than one discipline regardless of whether the disciplines are compatible or not.

Sample algorithms for the complete discipline resolution process are listed in Annex F.

7.4.4.1 Basic discipline resolution algorithm

In this mode (the default), both continuous and discrete disciplines propagate up the hierarchy to meet one another. At each level of the hierarchy where continuous and discrete meet for an undeclared net that net segment is declared continuous. This typically results in connect modules being inserted higher up the design hierarchy.

In the example shown in Figure 7-3, NetA, NetB, NetC, and NetD are undeclared interconnects.

connect cmos3 cmos4 resolveto cmos3; connect cmos1 cmos2 cmos3 resolveto cmos1;

Figure 7-3: Discipline resolution mode: basic

Using the basic mode of discipline resolution and the specified resolveto connect statements for this example results in the following:

—NetB resolves to cmos3 based on the first resolveto connect statement.

—NetA resolves to cmos1 based on the second resolveto connect statement.

—NetC resolves to electrical based on continuous (electrical) winning over discrete (cmos2).

—NetD resolves to electrical based on continuous (electrical) winning over discrete (cmos1).

7.4.4.2 Detail discipline resolution algorithm

In this mode continuous disciplines propagate up and then back down to meet discrete disciplines. Discrete disciplines do not propagate up the hierarchy. This can result in more connect modules being inserted lower down into discrete sections of the design hierarchy for added accuracy.

In the example shown in Figure 7-4, NetA, NetB, NetC, and NetD are undeclared interconnects.

connect cmos3 cmos4 resolveto cmos3; // discrete resolveto’s ignored connect cmos1 cmos2 cmos3 resolveto cmos1; // discrete resolveto’s ignored

Figure 7-4: Discipline resolution mode: detail

Using the detail mode of discipline resolution for this example results in the following:

—Continuous up: NetC resolves to electrical based on continuous (electrical) winning over discrete (cmos2).

—Continuous up: NetD resolves to electrical based on continuous (electrical) winning over undeclared.

—Continuous down: NetA resolves to electrical based on continuous (electrical) winning over undeclared.

—Continuous down: NetB resolves to electrical based on continuous (electrical) winning over undeclared.

The specified resolveto connect statements are ignored in this mode unless coercion (see 7.8.1) is used.

7.4.4.3 Coercing discipline resolution

Connect module insertion can be affected by coercion i.e., declaring disciplines for the interconnect in the hierarchy. If an interconnect is assigned a discipline, that discipline shall be used unless the resolveto connect statement overrides the discipline.