Добавил:
Upload Опубликованный материал нарушает ваши авторские права? Сообщите нам.
Вуз: Предмет: Файл:
VAMS-LRM-2-3-1.pdf
Скачиваний:
43
Добавлен:
05.06.2015
Размер:
3.73 Mб
Скачать

Accellera

 

Version 2.3.1, June 1, 2009

VERILOG-AMS

11.6.4 Ports

module

ports

port

vpiParent

vpiBit

port bit

-> connected by name bool: vpiConnByName

-> delay (mipd)

vpi_get_delays() vpi_put_delays()

-> direction

int: vpiDirection

-> explicitly named bool: vpiExplicitName

-> index

int: vpiPortIndex

-> location

int: vpiLineNo str: vpiFile

-> name

str: vpiName str: vpiFullName

-> scalar

bool: vpiScalar

-> size

int: vpiSize

-> vector

bool: vpiVector

NOTES

expr

vpiHighConn

expr

vpiLowConn

nodes

1—vpiHighConn shall indicate the hierarchically higher (closer to the top module) port connection.

2—vpiLowConn shall indicate the lower (further from the top module) port connection.

3—Properties scalar and vector shall indicate if the port is 1 bit or more than 1 bit. They shall not indicate anything about what is connected to the port.

4—Properties index and name shall not apply for port bits.

5—If a port is explicitly named, then the explicit name shall be returned. If not, and a name exists, that name shall be returned. Otherwise, NULL shall be returned.

6—vpiPortIndex can be used to determine the port order.

Copyright © 2009 Accellera Organization, Inc.

256

Analog and Mixed-signal Extensions to Verilog HDL

11.6.5 Nodes

module

nodes

node

branches vpiParent

nets

 

vpiBit

 

node bit

discipline

-> implicitly declared bool: vpiImplicitDecl

-> location

int: vpiLineNo str: vpiFile

-> name

str: vpiName str: vpiFullName

-> scalar

bool: vpiScalar

-> size

int: vpiSize

-> vector

bool: vpiVector

Accellera

Version 2.3.1, June 1, 2009

expr

vpiLeftRange

expr

vpiRightRange

expr

vpiIndex

NOTES

1—Properties scalar and vector shall indicate if the node is 1 bit or more than 1 bit.

257

Copyright © 2009 Accellera Organization, Inc. All rights reserved.

Accellera

 

Version 2.3.1, June 1, 2009

VERILOG-AMS

11.6.6 Branches

module

 

 

 

branches

vpiLeftRange

nodes

branch

vpiRightRange

vpiParent

 

vpiPosNode

 

 

nodes

 

 

vpiNegNode

 

 

Discipline

 

vpiIndex

vpiBit

 

 

branch

vpiFlow

 

 

-> location

 

vpiPotential

int: vpiLineNo

 

 

str: vpiFile

 

 

-> name

str: vpiName str: vpiFullName

-> scalar

bool: vpiScalar

-> size

int: vpiSize

-> vector

bool: vpiVector

expr

expr

expr

Quantity

Quantity

NOTE—Properties scalar and vector shall indicate if the branch is 1 bit or more than 1 bit.

Copyright © 2009 Accellera Organization, Inc.

258

Analog and Mixed-signal Extensions to Verilog HDL

11.6.7 Quantities

 

 

 

Quantities

Branches

 

 

Quantity

 

 

 

 

vpiParent

vpiBranch

 

 

 

 

 

Nature

 

 

 

 

vpiBit

 

 

 

 

 

 

 

 

 

Quantity

-> implicitly declared bool: vpiImplicitDecl

-> real value vpi_get_analog_value()

-> imaginary value vpi_get_analog_value()

-> scalar

bool: vpiScalar

-> size

int: vpiSize

-> vector

bool: vpiVector

-> source

bool: vpiSource

-> equation target

bool: vpiEquationTarget

Accellera

Version 2.3.1, June 1, 2009

expr

vpiLeftRange

expr

vpiRightRange

Contribs

expr

vpiIndex

259

Copyright © 2009 Accellera Organization, Inc. All rights reserved.

Соседние файлы в предмете [НЕСОРТИРОВАННОЕ]