a)The analog simulator advances time by calculating a sequence of solutions. Each solution has an associated time which, unlike the digital time, is not constrained to a particular minimum granularity.

b)The analog simulator can not tell for certain the time when the next solution converges. Thus, it can tell the time of the most recently calculated solution, but not the time of the next solution.

c)In general, the analog solution is a function of one or more previous solutions. Having calculated the solution for a given time, the analog simulator can either accept or reject that solution; it cannot calculate a solution for a future time until it has accepted the solution for the current time.

3)Analog to digital events

a)Analog to digital events are generated by conversion elements (which are analog/digital behavioral models) when evaluated by the analog simulator.

b)Analog events (e.g., cross, initial_step, and final_step) cause an analog solution of the time where they occur.

c)Thus, any analog to digital event is generated as the result of a particular transient solution. This means events can stay associated with the solution that produced them until they are passed to the digital simulator. Until then, they can be rejected along with the solution, if it is rejected.

4)Digital to analog events shall cause an analog solution of the time where they occur.

8.4 Scheduling semantics for the digital engine

The scheduling semantics for Verilog-HDL simulation are outlined in Clause 11 of IEEE std 1364-2005 Verilog HDL.

The digital engine of a Verilog-AMS mixed-signal simulator shall comply with that section except for the changes outlined in this section.

For mixed-signal simulation, the major change from Clause 11 of IEEE std 1364-2005 Verilog HDL is that two new types of event must be supported by the event queue called the explicit D2A (digital-to-analog) event, and the analog macro-process event.

Explicit D2A events are created when a digital event occurs to which an analog block is explicitly sensitive. An analog block is explicitly sensitive to event expressions mentioned in an event control statement in that analog block.

Similarly, there is also the concept of the implicit D2A event that is created when a digital variable to which an analog block is implicitly sensitive changes value. An analog block is implicitly sensitive to all digital variable references that are not guarded by event control statements in that analog block.

An analog macro-process event is also created when either type of D2A event occurs. The analog macroprocess event is associated with the analog macro-process that is sensitive to the D2A event. An analog macro-process event is evaluated by calling the analog engine to solve it. Note that implicit D2A events are not added to the stratified event queue, but as they directly cause an analog macro-process event, they effectively force a digital-analog synchronization when they occur.

8.4.1 The stratified event queue

The Verilog event queue is logically segmented into seven different regions. Events are added to any of the seven regions but are only removed from the active region. Regions 1b and 3b have been added for mixedsignal simulation.

1.Events that occur at the current simulation time and can be processed in any order. These are the active events.

1b. Explicit D2A events that occur at the current simulation time shall be processed after all the active events are processed.

2.Events that occur at the current simulation time, but that shall be processed after all the active and explicit D2A events are processed. These are the inactive events.

3.Events that have been evaluated during some previous simulation time, but that shall be assigned at this simulation time after all the active, explicit D2A and inactive events are processed. These are the non blocking assign update events.

3b. Analog macro-process events shall be processed after all active, explicit D2A events, inactive events and non blocking assign update events are processed.

4.Events that shall be processed after all the active, explicit D2A, inactive, non blocking assign update events and analog macro-process events are processed. These are the monitor events.

5.Events that occur at some future simulation time. These are the future events. Future events are divided into future inactive events and future non blocking assignment update events.

The processing of all the active events is called a simulation cycle.

The freedom to choose any active event for immediate processing is an essential source of nondeterminism in the IEEE std 1364-2005 Verilog HDL.

An explicit zero delay (#0) requires that the process be suspended and added as an inactive event for the current time so that the process is resumed in the next simulation cycle in the current time.

A nonblocking assignment (see 9.2.2 of IEEE std 1364-2005 Verilog HDL) creates a non blocking assign update event, scheduled for current or a later simulation time.

The $monitor, $strobe and $debug system tasks (see 17.1 of IEEE std 1364-2005 Verilog HDL) create monitor events for their arguments. These events are continuously re-enabled in every successive time step. The monitor events are unique in that they cannot create any other events.

The call back procedures scheduled with PLI routines such as tf_synchronize() (see Section 25.58 of IEEE 1364-2001) or vpi_register_cb(cb_readwrite) (see 27.33 of IEEE std 1364-2005 Verilog HDL) shall be treated as inactive events.

Note that A2D events must be analog event controlled statements ( e.g., @cross, @timer). These are scheduled just like other event controlled statements in Verilog-HDL (e.g., @posedge).

8.4.2 The Verilog-AMS digital engine reference model

In all the examples that follow, T refers to the current simulation time of the digital engine, and all events are held in the event queue, ordered by simulation time.

while (there are events){ if (no active events){

if (there are inactive events){ activate all inactive events;

else if (there are explicit D2A events) { activate all explicit D2A events;