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Accellera

 

Version 2.3.1, June 1, 2009

VERILOG-AMS

Example 3

connect cmosA2d split #(.r(30k) input electrical, output cmos02u;

performs three functions:

1)Connects an instance of cmosA2d module between a signal with electrical discipline and the input port with cmos02u discipline, or an output port with electrical discipline and the signal with cmos02u discipline;

2)Sets the value of the parameter r to 30k; and

3)Uses one module instance for each input port.

If there are many output ports where this rule applies, by definition there is no segmentation of the signal between these ports, since the ports have discipline electrical (an analog discipline).

Example 4

connect cmosA2d merged #(.r(15k) input electrical, output cmos04u;

does three things:

1)Connects an instance of cmosA2d module between a signal with electrical discipline and an input port with cmos04u discipline, or an output port with electrical discipline and a signal with cmos4u discipline;

2)Sets the value of the parameter r to 15k; and

3)Uses one module instance regardless of the number of ports.

7.8.4 Rules for driver-receiver segregation and connect module selection and insertion

Driver-receiver segregation and connect module insertion is a post elaboration operation. It depends on a complete hierarchical examination of each signal in the design, i.e., an examination of the signal in all the contexts through which it passes. If the complete hierarchy of a signal is digital, i.e., the signal has a digital discipline in all contexts through which is passes, it is a digital signal rather than a mixed signal. Similarly, if the complete hierarchy of a signal is analog, it is an analog signal rather than a mixed signal. Rules for driver-receiver segregation and connect module insertion apply only to mixed signals, i.e., signals which have an analog discipline in one or more of the contexts through which they pass and a digital discipline in one or more of the contexts. In this case, context refers to the appearance of a signal in a particular module instance.

For a particular signal, a module instance has a digital context if the signal has a digital discipline in that module or an analog context if the signal has an analog discipline. The appearance of a signal in a particular context is referred to as a segment of the signal. In general, a signal in a fully elaborated design consists of various segments, some of which can be analog and some of which can be digital.

A port represents a connection between two net segments of a signal. The context of one of the net segments is an instantiated module and the context of the other is the module which instantiates it. The segment in the instantiated module is called the lower or formal connection and the segment in the instantiating module is the upper or actual connection. A connection element is selected for each port where one connection is analog and the other digital.

The following rules govern driver-receiver segregation and connect module selection. These rules apply only to mixed signals.

1)A mixed signal is represented in the analog domain by a single node, regardless of how its analog contexts are distributed hierarchically.

Copyright © 2009 Accellera Organization, Inc.

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