// The following is illegal for P=32 initial

$displayb({32-P{1’b1}}, a[P-1:0]);

When a replication expression is evaluated, the operands shall be evaluated exactly once, even if the replication constant is zero. For example:

result = {4{func(w)}} ;

would be computed as:

y = func(w) ;

result = {y, y, y, y} ;

4.3 Built-in mathematical functions

Verilog-AMS HDL supports both the standard and transcendental mathematical functions. Both the IEEE std 1364-2005 Verilog HDL system function syntax style and the traditional Verilog-AMS HDL style are supported. Users are encouraged to adopt the IEEE std 1364-2005 Verilog HDL system function style when using the mathematical functions but the traditional Verilog-AMS HDL style will continue to be supported for backwards compatibility. The following tables Table 4-14 and Table 4-15 show both syntax styles as well as the equivalent C function.

4.3.1 Standard mathematical functions

The standard mathematical functions supported by Verilog-AMS HDL are shown in Table 4-14. The operands shall be numeric (integer or real). For min(), max(), and abs(), if either operand is real, both are converted to real, as is the result. All other arguments are converted to real.

Table 4-14—Standard functions