1’b0: avar = 0;

1’bz: avar = 2.5; // high impedance - float value endcase

Accessing digital net and digital binary constant operands are supported within analog context expressions. It is an error if these operands return x or z bit values when solved. It will be an error if the value of the digital variable being accessed in the analog context goes either to x or z.

Example:

module converter(dnet, anet); output dnet;

inout anet; reg dnet;

electrical anet; integer var1; real var2;

initial begin dnet = 1’b1;

#50 dnet = 1’bz; $finish;

endmodule

The syntax for the features that support x and z comparisons in a continuous context is defined in 2.6 and 5.8.3. Support for x and z is limited in the analog blocks as defined above.

NOTE—Consult section 5.1.8 in IEEE std 1364-2005 Verilog HDL for a description of the semantics of these operators.

7.3.2.1 Special floating point values

Floating point arithmetic can produce special values representing plus and minus infinity and Not-a-Number (NaN) to represent a bad value. While use of these special numbers in digital expressions is not an error, it is illegal to assign these values to a branch through contribution in the analog context.

7.3.3 Accessing continuous nets and variables from a discrete context

All continuous nets can be probed from a discrete context using access functions. All probes which are legal in a continuous context of a module are also legal in the discrete context of a module.

The following example accesses the continuous net V(in) from the discrete context is.

module sampler (in, clk, out); inout in;

input clk; output out; electrical in; wire clk;

reg out;

always @(posedge clk) out = V(in);

endmodule

Continuous variables can be accessed for reading from any discrete context in the same module where these variables are declared. Because the discrete domain can fully represent all continuous types, a continuous variable is fully visible when it is read in a discrete context. If the current time in the continuous and discrete kernels differ, interpolation is used to determine the value to be used in the discrete context for the continuous variable unless the value of the continuous variable was last assigned in an analog event statement. In this case, the value used in the digital context is exactly the same as the last value assigned to the continuous variable.

7.3.4 Detecting discrete events in a continuous context

Discrete events can be detected in a Verilog-AMS HDL continuous context. The arguments to discrete events in continuous contexts are in the discrete context. A discrete event in a continuous context is nonblocking like the other event types allowed in continuous contexts. The syntax for events in a continuous context is shown in Syntax 7-2.

analog_event_control_statement ::= analog_event_control analog_event_statement // from A.6.5

analog_event_control ::=

@ hierarchical_event_identifier | @ ( analog_event_expression )

analog_event_expression ::= expression

| posedge expression | negedge expression

| hierarchical_event_identifier

| initial_step [ ( " analysis_identifier "{ , " analysis_identifier " } ) ] | final_step [ ( " analysis_identifier " { , " analysis_identifier " } ) ]

| analog_event_functions

| analog_event_expression or analog_event_expression

analog_event_functions ::=

cross ( analog_expression [ , analog_expression_or_null

[ , constant_expression_or_null [ , constant_expression_or_null [ , analog_expression ] ] ] ] ) | above ( analog_expression [ , constant_expression_or_null

[ , constant_expression_or_null [ , analog_expression ] ] ] ) | timer ( analog_expression [ , analog_expression_or_null

[ , constant_expression_or_null [ , analog_expression ] ] ] )

analog_event_statement ::=

{ attribute_instance } analog_loop_statement | { attribute_instance } analog_case_statement

| { attribute_instance } analog_conditional_statement | { attribute_instance } analog_procedural_assignment | { attribute_instance } analog_event_seq_block

| { attribute_instance } analog_system_task_enable

7.3.5 Detecting continuous events in a discrete context

In Verilog-AMS HDL, monitored continuous events can be detected in a discrete context. The arguments to these events are in the continuous context. A continuous event in a discrete context is blocking like other discrete events. The syntax for analog events in a discrete context is shown in Syntax 7-3.