I(a,c) <+ ddt(qdio); end

endmodule

9.18 Hierarchical parameter system functions

Verilog AMS HDL adds system functions that can return hierarchically inherited values in a particular instance.

The syntax for these functions are shown in Syntax 9-13.

hierarchical_system_parameter_functions ::= $mfactor

| $xposition | $yposition | $angle

| $hflip | $vflip

Syntax 9-13—Syntax for the hierarchical parameter system functions

$mfactor is the shunt multiplicity factor of the instance, that is, the number of identical devices that should be combined in parallel and modeled.

$xposition and $yposition are the offsets, in meters, of the location of the center of the instance.

$hflip and $vflip are used to indicate that the instance has been mirrored about its center, and $angle indicates that the instance has been rotated some number of degrees in the counter-clockwise directions.

The value returned for each of these functions is computed by combining values from the top of the hierarchy down to the instance making the function call. The rules for combining the values are given in Table 9-28. The top-level value is the starting value at the top of the hierarchy. If a module is instantiated without specifying a value of one of these system parameters (using any of the methods in 6.3), then the value of that system parameter will be unchanged from the instantiating module. If a value is specified, then it is combined with the value from the instantiating module according to the appropriate rule from Table 9-28: the subscript “specified” indicates the value specified for the instance, and the subscript “hier” indicates the value obtained by traversing the hierarchy from the top to the instantiating module.

Table 9-28— Hierarchical parameter values

Table 9-28— Hierarchical parameter values (continued)

For example, when a module makes a call to $mfactor, the simulator computes the product of the multiplicity factor specified for the instance (or 1.0, if no override was specified) times the value for the parent module that instantiated the module, times the parent’s parent’s value, and so on, until the top level is reached.

Note that $angle is specified and returned in degrees, but the trigonometric functions of 4.3.2 operate in radians.

Example 1

module test_module(p,n); inout p,n;

electrical p,n; module_a A1(p,n);

endmodule

module module_a(p,n); inout p,n; electrical p,n;

module_b #(.$mfactor(2)) B1(p,n); // mfactor = 3 * 2 endmodule

module module_b(p,n); inout p,n; electrical p,n;

module_c #(.$mfactor(7)) C1(p,n); // mfactor = 3 * 2 * 7 = 42 endmodule

// linear resistor module module_c(p,n);

inout p,n; electrical p,n; parameter r=1.0;

(* desc = "effective resistance" *) real reff; analog begin

I(p,n) <+ V(p,n)/r; // mfactor scaling of currents // handled automatically

reff = r / $mfactor; // the effective resistance = 1/42 end

endmodule

shows how the effect mfactor of an instance, test_module.A1.B1.C1 of a linear resistance is determined.

Example 2

module test_module(p,n);

inout p,n; electrical p,n; module_a A1(p,n);

endmodule

module module_a(p,n); inout p,n; electrical p,n;

module_b #(.$xposition(1u)) B1(p,n); // xposition=1.1u + 1u endmodule

module module_b(p,n); inout p,n; electrical p,n;

module_c #(.$xposition(2u)) C1(p,n); // xposition=1.1u + 1u + 2u = 4.1u endmodule

// linear resistor module module_c(p,n);

inout p,n; electrical p,n; parameter r=1.0; analog begin

// Expected value of xposition=4.1e-6 if ($xposition == 4.1u)

I(p,n) <+ V(p,n)/1.0; else

I(p,n) <+ V(p,n)/2.0;

end endmodule

9.19 Explicit binding detection system functions

Verilog AMS HDL adds functions that can be used to check whether a parameter or port binding was explicity made.

The behavioral code of a module can depend on the way in which it was instantiated. The hierarchy detection functions shown in Syntax 9-14 may be used to determine information about the instantiation.

genvar_system_function ::=

$param_given ( module_parameter_identifier ) | $port_connected ( port_scalar_expression )

Syntax 9-14—Syntax for the hierarchy detection functions

Note that the return values of these functions shall be constant during a simulation; the value is fixed during elaboration. As such, these functions can be used in genvar expressions controlling conditional or looping behavior of the analog operators of 4.5.

The $param_given() function can be used to determine whether a parameter value was obtained from the default value in its declaration statement or if that value was overridden. The $param_given() function takes a single argument, which must be a parameter identifier. The return value shall be one (1) if the parameter was overridden, either by a defparam statement or by a module instance parameter value assignment, and zero (0) otherwise.

The following example sets the variable temp to represent the device temperature. Note that $temperature is not a constant_expression, so it cannot be used as the default value of the parameter tdevice. It is important to be able to distinguish the case where tdevice has its default value (say, 27) from the declaration statement from the case where the value 27 was in fact specified as an override, if the simulation is performed at a different temperature.

if ($param_given(tdevice))

temp = tdevice + ‘P_CELSIUS0; else

temp = $temperature;

Module ports need not be connected when the module is instantiated. The $port_connected() function can be used to determine whether a connection was specified for a port. The $port_connected() function takes one argument, which must be a port identifier. The return value shall be one (1) if the port was connected to a net (by order or by name) when the module was instantiated, and zero (0) otherwise. Note that the port may be connected to a net that has no other connections, but $port_connected() shall still return one.

In the following example, $port_connected() is used to skip the transition filter for unconnected nodes. In module twoclk, the instances of myclk only have connections for their vout_q ports, and thus the filter for vout_qbar is not implemented for either instance. In module top, the vout_q2 port is not connected, so that the vout_q port of topclk1.clk2 is not ultimately used in the circuit; however, the filter for vout_q of clk2 is implemented, because it vout_q is connected on clk2’s instantiation line.

module myclk(vout_q, vout_qbar); output vout_q, vout_qbar; electrical vout_q, vout_qbar;

parameter real tdel = 3u from [0:inf); parameter real trise = 1u from (0:inf); parameter real tfall = 1u from (0:inf); parameter real period = 20u from (0:inf); integer q;

analog begin

@(timer(0, period)) q = 0;

@(timer(period/2, period)) q = 1;

if ($port_connected(vout_q))

V(vout_q) <+ transition( q, tdel, trise, tfall); else

V(vout_q) <+ 0.0;

if ($port_connected(vout_qbar))

V(vout_qbar) <+ transition( !q, tdel, trise, tfall); else

V(vout_qbar) <+ 0.0;

end endmodule

module twoclk(vout_q1, vout_q2); output vout_q1, vout_q2; electrical vout_q1, vout_q1b; myclk clk1(.vout_q(vout_q1)); myclk clk2(.vout_q(vout_q2));

endmodule

module top(clk_out); output clk_out;