C.2 Lexical conventions

With the exception of certain keywords required for Verilog-AMS HDL, 2. shall be applicable to both Ver- ilog-A and Verilog-AMS HDL. All Verilog-AMS HDL keywords shall be supported by Verilog-A as reserved words, but IEEE std 1364-2005 Verilog HDL and Verilog-AMS HDL specific keywords are not used in Verilog-A. The following Verilog-AMS HDL keywords are not required to be supported for a fully compliant Verilog-A subset:

From 2.6, Numbers: support for X and Z values is limited in the analog block to the mixed signal context, as defined in 7.3.2. In the same paragraph, the use of the question mark character as an alternative for z is also limited to the mixed signal context.

From 2.8.2, Keywords: certain keywords are not applicable in Verilog-A, as defined in Annex C.15.

C.3 Data types

The data types of Clause 3 are applicable to both Verilog-AMS HDL and Verilog-A with the following exceptions:

—From 3.6.2.2, Domain binding: the domain binding type discrete shall be an error in Verilog-A.

—From 3.7, Real net declarations: the wreal data type is not supported in Verilog-A.

—From 3.8, Default discipline: the `default_discipline compiler directive is not supported in Verilog-A. All Verilog-A modules shall have a discipline defined for each module.

This feature allows the use of digital modules in Verilog-AMS HDL without editing them to add a discipline.

C.4 Expressions

The expressions defined in Clause 4 are applicable to both Verilog-AMS HDL and Verilog-A with the following exception:

The case equality operators (===, !==) are not supported in Verilog-A.

C.5 Analog signals

The signals defined in 5.4 are applicable to both Verilog-AMS HDL and Verilog-A.

C.6 Analog behavior

The analog behavior defined in Clause 5 are applicable to both Verilog-AMS HDL and Verilog-A with the following exceptions:

—No digital behavior or events are supported in Verilog-A.

—casex and casez are not supported in Verilog-A.

C.7 Hierarchical structures

The hierarchical structure defined in Clause 6 is applicable to both Verilog-AMS HDL and Verilog-A, except support for real value ports is only applicable to Verilog-AMS HDL and IEEE std 1364-2005 Verilog HDL (see 6.5.3).

C.8 Mixed signal

Clause 7only applies to Verilog-AMS HDL.

C.9 Scheduling semantics

The analog simulation cycle is applicable to both Verilog-AMS HDL and Verilog-A. The mixed-signal simulation cycle from 8.2 is only applicable to Verilog-AMS HDL.

C.10 System tasks and functions

All system tasks and functions in Clause 9 that are applicable in the analog context are applicable to Ver- ilog-A.

C.11 Compiler directives

The compiler directives of Clause 10 are applicable to both Verilog-AMS HDL and Verilog-A.

C.12 Using VPI routines

The analog behavior defined in Clause 11 is applicable to both Verilog-AMS HDL and Verilog-A.

C.13 VPI routine definitions

The analog behavior defined in Clause 12 is applicable to both Verilog-AMS HDL and Verilog-A.

C.14 Analog language subset

This annex (Annex C) defines the differences between Verilog-AMS HDL and Verilog-A. Annex A defines the BNF for Verilog-AMS HDL.

C.15 List of keywords

The keywords in Annex B are the complete set of Verilog-AMS HDL keywords, including those from IEEE std 1364-2005 Verilog HDL. The following keywords as defined in this LRM are not used by Verilog-A:

connect connectmodule connectrules

driver_update endconnectrules merged net_resolution resolvedto split

wreal

NOTE—All keywords of Verilog-AMS HDL are reserved words for Verilog-A.

C.16 Standard definitions

The definitions of Annex D are applicable to both Verilog-AMS HDL and Verilog-A, with the exception of those disciplines with a domain of discrete. A Verilog-A implementation shall silently ignore any definition of a discipline with a domain of discrete.

C.17 SPICE compatibility

Annex E defines the SPICE compatibility for both Verilog-A and Verilog-AMS HDL.

C.18 Changes from previous Verilog-A LRM versions

Annex G describes the changes from previous LRM versions for both Verilog-A and Verilog-AMS HDL.

C.19 Obsolete functionality

Annex G also describes the statements that are no longer supported in the current version of Verilog-AMS HDL as well as the analog language subset.

Annex D

(normative)

Standard definitions

This annex contains the standard definition packages (disciplines.vams, constants.vams and driver_access.vams) for Verilog-AMS HDL.

D.1 The disciplines.vams file

`ifdef DISCIPLINES_VAMS `else

`define DISCIPLINES_VAMS 1

//

// Natures and Disciplines

//

discipline \logic ; domain discrete;

enddiscipline

discipline ddiscrete; domain discrete;

enddiscipline

/*

*Default absolute tolerances may be overridden by setting the

*appropriate _ABSTOL prior to including this file

*/

//Electrical

//Current in amperes nature Current;

// Potential in volts nature Voltage;

ddt_nature = Voltage; `ifdef FLUX_ABSTOL

//Conservative discipline discipline electrical;

potential Voltage; flow Current;

enddiscipline

//Signal flow disciplines discipline voltage;

potential Voltage; enddiscipline

discipline current; flow Current;

enddiscipline

//Magnetic

//Magnetomotive force in Ampere-Turns. nature Magneto_Motive_Force;

//Conservative discipline discipline magnetic;

potential Magneto_Motive_Force; flow Flux;

enddiscipline

//Thermal

//Conservative discipline discipline thermal;

potential Temperature; flow Power;

enddiscipline

//Kinematic

//Position in meters

nature Position;

`ifdef POSITION_ABSTOL

// Velocity in meters per second nature Velocity;

// Acceleration in meters per second squared nature Acceleration;

// Conservative disciplines discipline kinematic;

potential Position; flow Force;

enddiscipline

discipline kinematic_v; potential Velocity; flow Force;

enddiscipline

//Rotational

//Angle in radians nature Angle;

`ifdef ANGLE_ABSTOL

// Angular Velocity in radians per second nature Angular_Velocity;