6.5.3 Real valued ports

Verilog-AMS HDL supports ports which are declared to be real-valued and have a discrete-time discipline. This is done using the net type wreal (defined in 3.7). There can be a maximum of one driver of a real-val- ued net.

Examples:

module top(); wreal stim; reg clk;

wire [1:8] out;

testbench tb1 (stim, clk); a2d dut (out, stim, clk);

initial clk = 0; always #1 clk = ~clk;

endmodule

module testbench(wout, clk); output wout;

input clk; real out; wire clk; wreal wout;

assign wout = out;

always @(posedge clk) begin out = out + $abstime;

end endmodule

module a2d(dout, in, clk); output [1:8] dout; input in, clk;

wreal in; wire clk;

reg [1:8] dout; real residue; integer i;

always @(negedge clk) begin residue = in;

for (i = 8; i >= 1; i = i - 1) begin if (residue > 0.5) begin

dout[i] = 1’b1;

residue = residue - 0.5; end

else begin dout[i] = 1’b0;

end

residue = residue*2; end

end endmodule

6.5.4 Connecting module ports by ordered list

One way to connect the ports listed in a module instantiation with the ports defined by the instantiated module is via an ordered list—that is, the ports listed for the module instance shall be in the same order as the ports listed in the module definition.

Examples:

module adc4 (out, rem, in); output [3:0] out; output rem; input in;

electrical [3:0] out; electrical in, rem, rem_chain;

adc2 hi2 (out[3:2], rem_chain, in); adc2 lo2 (out[1:0], rem, rem_chain);

endmodule

module adc2 (out, remainder, in); output [1:0] out; output remainder; input in;

electrical [1:0] out; electrical in, remainder, r;

adc hi1 (out[1], r, in);

adc lo1 (out[0], remainder, r); endmodule

module adc (out, remainder, in); output out, remainder;

input in;

electrical out, in, remainder; integer d;

analog begin

d = (V(in) > 0.5); V(out) <+ transition(d);

V(remainder) <+ 2.0 * V(in); if (d)

V(remainder) <+ -1.0;

end endmodule

6.5.5 Connecting module ports by name

The second way to connect module ports consists of explicitly linking the two names for each side of the connection — specify the name used in the module definition, followed by the name used in the instantiating module. This compound name is then placed in the list of module connections.

The following rules apply:

—The name of port shall be the name specified in the module definition.

—The name of port cannot be a bit select or a part select.

—The port expression shall be the name used by the instantiating module and can be one of the following:

— a simple net identifier