Добавил:
Upload Опубликованный материал нарушает ваши авторские права? Сообщите нам.
Вуз: Предмет: Файл:
VAMS-LRM-2-3-1.pdf
Скачиваний:
43
Добавлен:
05.06.2015
Размер:
3.73 Mб
Скачать

 

Accellera

Analog and Mixed-signal Extensions to Verilog HDL

Version 2.3.1, June 1, 2009

If a dynamic expression is passed as an argument which expects a constant expression, the value of the dynamic expression at the start of the analysis defaults to the constant value of the argument. Any further change in value of that expression is ignored during the iterative analysis.

4.5.15 Restrictions on analog operators

Analog operators are subject to several important restrictions because they maintain their internal state. It is important to ensure that all analog operators are evaluated every iteration of a simulation to ensure that the internal state is maintained. The analog operator ddx() is the only exception to this rule as it does not require an internal state to be maintained. All analog operators are considered to have no state history prior to time t == 0.

Analog operators shall not be used inside conditional (if, case, or ?:) statements unless the conditional expression controlling the statement consists of terms which can not change their value during the course of a simulation.

Analog operators shall not be used inside event triggered statements.

Analog operators are not allowed in the repeat, while and non-genvar for looping statements.

Analog operators can only be used inside an analog block; they can not be used inside an initial or always block, or inside a user defined function.

It is illegal to specify a null argument in the argument list of an analog operator, except as specified elsewhere in this document.

These restrictions help prevent usage which could cause the internal state to be corrupted or become out-of- date, which results in anomalous behavior.

4.6 Analysis dependent functions

This section describes the analysis() function, which is used to determine what type of analysis is being performed, and the small-signal source functions. The small-signal source functions only affect the behavior of a module during small-signal analyses. The small-signal analyses provided by SPICE include the AC and noise analyses, but others are possible. When not active, the small-signal source functions return zero (0).

4.6.1 Analysis

The analysis() function takes one or more string arguments and returns one (1) if any argument matches the current analysis type. Otherwise it returns zero (0). The general form is:

analysis ( analysis_list )

There is no fixed set of analysis types. Each simulator can support its own set. However, simulators shall use the names listed in Table 4-21 to represent analyses which are similar to those provided by SPICE..

 

Table 4-21—Analysis types

 

 

Name

Analysis description

 

 

"ac"

.AC analysis

"dc"

.OP or .DC analysis (single point or dc sweep analysis)

"noise"

.NOISE analysis

"tran"

.TRAN analysis

"ic"

The initial-condition analysis which precedes a transient analysis.

79

Copyright © 2009 Accellera Organization, Inc. All rights reserved.

Accellera

 

Version 2.3.1, June 1, 2009

VERILOG-AMS

 

Table 4-21—Analysis types (continued)

 

 

Name

Analysis description

 

 

"static"

Any equilibrium point calculation, including a DC analysis as well as those that precede

 

another analysis, such as the DC analysis which precedes an AC or noise analysis, or the

 

IC analysis which precedes a transient analysis.

 

 

"nodeset"

The phase during an equilibrium point calculation where nodesets are forced.

Any unsupported type names are assumed to not be a match.

Table 4-22 describes the implementation of the analysis function. Each column shows the return value of the function. A status of one (1) represents True and zero (0) represents False.

Table 4-22—Analysis function implementation

Analysis

Argument

DC

 

Sweepa

TRAN

 

AC

NOISE

d1 d2 dN

op Tran

 

op

op AC

 

 

 

 

AC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

First part of "static"

"nodeset"

1

1

0

0

1

0

1

0

1

0

when nodesets are enforced

 

 

 

 

 

 

 

 

 

 

 

Initial DC state

"static"

1

1

1

1

1

0

1

0

1

0

Initial condition

"ic"

0

0

0

0

1

0

0

0

0

0

DC

"dc"

1

1

1

1

0

0

0

0

0

0

Transient

"tran"

0

0

0

0

1

1

0

0

0

0

Small-signal

"ac"

0

0

0

0

0

0

1

1

0

0

Noise

"noise"

0

0

0

0

0

0

0

0

1

1

aSweep refers to a dc analysis in which a parameter is swept through multiple values. d1, d2 and dN above refer to dc points within the same sweep analysis.

Using the analysis() function, it is possible to have a module behave differently depending on which analysis is being run.

For example, to implement nodesets or initial conditions using the analysis function and switch branches, use the following.

if (analysis("ic"))

V(cap) <+ initial_value; else

I(cap) <+ ddt(C*V(cap));

4.6.2 DC analysis

Verilog-AMS supports a single-point dc analysis and also a multipoint dc sweep analysis in which multiple dc points are computed over a sweep of parameter values. An operating point analysis is done for each dc point in the sweep. A single-point dc analysis is the same as an operating point analysis. The analysis("dc") and analysis("static") function calls shall return true for a single-point dc analysis and also for every dc point in a sweep analysis. The analysis("nodeset") function call shall return true only during the phase of an operating point analysis in which nodeset values are enforced; that phase may

Copyright © 2009 Accellera Organization, Inc.

80

Соседние файлы в предмете [НЕСОРТИРОВАННОЕ]