3. Data types

3.1 Overview

Verilog-AMS HDL supports integer, genvar, real, and parameter data types as found in IEEE std 1364-2005 Verilog HDL. It includes the string data type defined by IEEE std 1800-2005 SystemVerilog. It also modifies the parameter data types and introduces array of real as an extension of the real data type. Plus, it extends the net data types to support a new type called wreal to model real value nets.

Verilog-AMS HDL introduces a new data type, called net_discipline, for representing analog nets and declaring disciplines of all nets and regs. The disciplines define the domain and the natures of potential and flow and their associated attributes for continuous domains.

3.2 Integer and real data types

The syntax for declaring integer and real is shown in Syntax 3-1.

An integer declaration declares one or more variables of type integer. These variables can hold values ranging from -231 to 231-1. Arrays of integers can be declared using a range which defines the upper and lower indices of the array. Both indices shall be constant expressions and shall evaluate to a positive integer, a negative integer, or zero (0).

Arithmetic operations performed on integer variables produce 2’s complement results.

A real declaration declares one or more variables of type real. The real variables are stored as 64-bit quantities, as described by IEEE std 754-1985, an IEEE standard for double precision floating point numbers.

Arrays of parameter can be declared using a range which defines the upper and lower indices of the array. Both indices shall be constant expressions and shall evaluate to a positive integer, a negative integer, or zero (0).

Integers are initialized at the start of a simulation depending on how they are used. Integer variables whose values are assigned in an analog context default to an initial value of zero (0). Integer variables whose values are assigned in a digital context default to an initial value of x. Real variables are initialized to zero (0) at the start of a simulation.