Since it is physically one wire in the design, Kirchoff’s current law applies to the whole signal, and it forms one node in analog simulation (see 3.6). Drivers in the digital domain are converted to contributions in the analog domain using auto-inserted digital-to-analog connection modules (D2As), and the signal value is calculated in the analog domain. Instead of determining the final digital receiver value of the signal by resolving all the digital drivers, the resolved analog signal is converted back to a digital value. A digital behavioral block that reads the value of a signal is a receiver, but since Verilog-AMS has no syntax that identifies multiple receivers within a module as distinct, the associated net can be viewed as a single receiver for the purposes of analog to digital conversion. Drivers are created by declaring a reg, instantiating a digital primitive or using a continuous assign statement. Since it is only possible to insert connect modules at port boundaries, when multiple continuous assign statements exist in a module, they are handled by a single connect module.

The drivers and receivers of a mixed signal are associated with their locally-declared net; the discipline of that net is used to determined which connection modules to use. The discipline of the whole signal is found by discipline resolution, as described in 7.4, and is used to determine the attributes of the node in simulation.

7.2.4 Mixed-signal and net disciplines

One job of the discipline of a continuous net is to specify the tolerance (abstol) for the potential of the associated node. A mixed signal can have a number of compatible continuous nets, with different continuous disciplines and different abstols. In this case, the abstol of the associated node shall be the smallest of the abstols specified in the disciplines associated with all the continuous nets of the signal.

If an undeclared net segment has multiple compatible disciplines connected to it, a connect statement shall specify which discipline to use during discipline resolution.

7.3 Behavioral interaction

Verilog-AMS HDL supports several types of block statements for describing behavior, such as analog blocks, initial blocks, and always blocks. Typically, non-analog behavior is described in initial and always blocks, assignment statements, or assign declarations. There can be any number of initial, always and analog blocks in a particular Verilog-AMS HDL module.

Nets and variables in the continuous domain are termed continuous nets and continuous variables respectively. Likewise nets, regs and variables in the discrete domain are termed discrete nets, discrete regs, and discrete variables. In Verilog-AMS HDL, the nets and variables of one domain can be referenced in the other’s context. This is the means for passing information between two different domains (continuous and discrete). Read operations of nets and variables in both domains are allowed from both contexts. Write operations of nets and variables are only allowed from the context of their domain.

Verilog-AMS HDL provides ways to:

—access discrete primaries (e.g., nets, regs, or variables) from a continuous context

—access continuous primaries (e.g., flows, potentials, or variables) from a discrete context

—detect discrete events in a continuous context

—detect continuous events in a discrete context

The specific time when an event from one domain is detected in the other domain is subject to the synchronization algorithm described in 7.3.6 and Clause 8. This algorithm also determines when changes in nets and variables of one domain are accessible in the other domain.

7.3.1 Accessing discrete nets and variables from a continuous context

Discrete nets and variables can be accessed from a continuous context. However, because the data types which are supported in continuous contexts are more restricted than those supported in discrete contexts, certain discrete types can not be accessed in a continuous context.

Table 7-1 lists how the various discrete net/variable types can be accessed from a continuous context.

Table 7-1—Discrete net/variable access from continuous context

The syntax for a Verilog-AMS HDL primary is defined in Syntax 7-1.