4.2.9 Bitwise operators

The bitwise operators perform bitwise manipulations on the operands—that is, the operator combines a bit in one operand with its corresponding bit in the other operand to calculate one bit for the result. The following logic tables (Table 4-9 — Table 4-13) show the results for each possible calculation.

Table 4-9—Bitwise binary and operator

Table 4-10—Bitwise binary or operator

Table 4-11—Bitwise binary exclusive or operator

Table 4-12—Bitwise binary exclusive nor operator

Table 4-13—Bitwise unary negation operator

~

01

10

When one or both operands are unsigned. the expression shall be interpreted as a comparison between unsigned values. If the operands are of unequal bit lengths, the smaller operand shall be zero-extended to the size of the larger operand.

When both operands are signed, the expression shall be interpreted as a comparision between signed values. If the operands are of unequal bit lengths, the smaller operand shall be sign-extended to the size of the larger operand.

4.2.10 Reduction operators

The reduction operators can not be used inside the analog block and only have meaning when used in the digital context. Information on these operators can also be found in the IEEE std 1364-2005 Verilog HDL.

4.2.11 Shift operators

There are two types of shift operators: the logical shift operators, << and >>, and the arithmetic shift operators, <<< and >>>. The arithmetic shift operators can not be used in an analog block. Further information on these operators can be found in IEEE std 1364-2005 Verilog HDL. The logical shift operators, << and >>, perform left and right shifts of their left operand by the number of bit positions given by the right operand. Both the << and >> shift operators fill the vacated bit positions with zeroes (0).The right operand is always treated as an unsigned number and has no effect on the signedness of the result.

Examples:

integer start, result; analog begin

start = 1;

result = (start << 2); end

In this example, the integer result is assigned the binary value 0100, which is 0001 shifted to the left two positions and zero-filled.

integer start, result; analog begin

start = 3;

result = (start >> 1); end

In this example, the integer result is assigned the binary value 0001, which is 0011 shifted to the right one position and zero-filled.

4.2.12 Conditional operator

The conditional operator, also known as ternary operator, is right associative and shall be constructed using three operands separated by two operators, as shown in Table 4-1.

The evaluation of a conditional operator begins with the evaluation of expression1. If expression1 evaluates to false (0), then expression3 is evaluated and used as the result of the conditional expression. If expression1 evaluates to true (any value other than zero (0)), then expression2 is evaluated and used as the result.

4.2.13 Concatenations

A concatenation is the result of the joining together of bits resulting from one or more expressions into a single value. The concatenation shall be expressed using the brace characters { and }, with commas separating the expressions within. It should not be confused with the array literal syntax '{ } which is array of values. Confusion can arise because { } is the array literal syntax in the C language whereas it means something very different in the Verilog HDL and Verilog-AMS HDL languages.

Unsized constant numbers shall not be allowed in concatenations. This is because the size of each operand in the concatenation is needed to calculate the complete size of the concatenation.

This example concatenates two expressions:

{1'b1, 3'b101}

It is equivalent to the following example:

{1'b1, 1'b1, 1'b0, 1'b1}

Its value is 4'b1101.

The next example concatenates three strings:

{ "hello", " ", "world" }

Its value is "hello world".

An operator that can be applied only to concatenations is replication, which is expressed by a concatenation preceded by a non-negative, non-x and non-z constant expression, called a replication constant, enclosed together within brace characters, and which indicates a joining together of that many copies of the concatenation. Unlike regular concatenations, expressions containing replications shall not appear on the left-hand side of an assignment and shall not be connected to output or inout ports.

The following example replicates w four times:

{4{w}} // This yields the same value as {w, w, w, w}

The next example illustrates a replication nested within a concatenation:

A replication operation may have a replication constant with a value of zero. This is useful in parameterized code. A replication with a zero replication constant is considered to have a size of zero and is ignored. Such a replication shall appear only within a concatenation in which at least one of the operands of the concatenation has a positive size. For example:

parameter P = 32;

//The following is legal for all P from 1 to 32 assign b[31:0] = { {32-P{1’b1}}, a[P-1:0] } ;

//The following is illegal for P=32 because the zero

//replication appears alone within a concatenation assign c[31:0] = { {{32-P{1’b1}}}, a[P-1:0] }