Virtuoso XL Layout Editor User Guide

Using the Virtuoso Custom Placer

placer’s only objective is to reduce overall wire length and to achieve a balanced placement.

Devices will tend to spread out using all the area allowed for placement.

The placement task for row-based designs typically involves these steps (explained in more detail in “Setting Placement Planning” on page 287):

1.Create component types to use in assigning devices to rows.

2.For MOS device-level designs, set the parameters for device chaining and folding.

3.(Optional) Generate layout data from the schematic for critical components with the interactive command Pick from Schematic. Make a preliminary placement of the critical components using the objectediting commands. If critical components are hand placed to their final placement, they can be “locked” in place during automatic placement to preserve the preplacement.

4.Generate layout and a preliminary placement for the remainder of the design using Gen From Source if you did not perform Step 3, or otherwise use Update Components and Nets.

5.Define rows for placement.

You can use component assisted mode only, a combination of assisted and user-defined, or just user-defined.

6.Assign component types to the appropriate rows.

7.Align objects to their respective rows.

Part of defining rows is to check that the component type, alignment, and orientation are set properly.

8.Specify the orientation of components with rows.

9.(Optional) Set confinement, grouping, and otherconstraints.

10.Place and constrain pins using the Place – Pin Placement command.

11.Run the automatic placer with the Place – Placer command to generate a placement.

12.(Optional) Update constraints and run Place – Placer again.

13.Repeat Step 12 as needed to further refine the placement.

Setting Up the Virtuoso XL Layout Editor for Placement

This section describes some variables you may want to set and some design style decisions you should make before you begin working with the placer.

Virtuoso XL Layout Editor User Guide

Using the Virtuoso Custom Placer

Identifying the Placement Translation Rules

The Virtuoso custom placer and the Virtuoso custom router both use a rules file to define how data should be translated between the Cadence design framework II (DFII) environment and the placement and routing environment. In general, the router requires more elaborate translation rules than the placer (because the router needs to know more about the design and use of routing resources). Rules you create for the router should work properly, unmodified, with the placer too.

Cadence recommends that you have a separate translation rules file for placement purposes. You will want to translate only the minimum amount of data. Extra data not used by the Virtuoso custom placer will dramatically affect the placer’s performance, especially with mixed design styles.

Note: For CMOS device level designs, diffusion layers must be translated as routing layers in order for Virtuoso custom placer to chain devices.

Placement translation rules can be stored in the technology file or in a separate ASCII file. Specify the ASCII file in theAuto Placer form.

Setting Cadence Design Framework II Environment Variables

To permit the placer to properly handle permutable pins, set the UNIX environment variable

CDS_Netlisting_Mode as follows:

setenv CDS_Netlisting_Mode Analog

or

setenv CDS_Netlisting_Mode Compatibility

Note: Do not set the netlisting mode to Compatibility if you will be chaining and folding devices.

If you do not have permutable pins in your design, and make no other use of CDF data, you can get faster netlisting performance by setting CDS_Netlisting_Mode to Digital:

setenv CDS_Netlisting_Mode Digital

Virtuoso XL Layout Editor User Guide

Using the Virtuoso Custom Placer

Setting Environment Variables for the Virtuoso Custom Router and Placer

Some of the .cdsenv file variables that you might set to control the Virtuoso custom router can disrupt operation of the placer:

■The enableAutoImport variable must be set to on by default. Check for this line in your .cdsenv file:

iccTranslator enableAutoImport boolean t

■The exportVersion variable, if set, must be set to the current version of the placer.

The system also checks the obsolete UNIX environment variable ICC_VERSION. The larger of the two values is used. To avoid problems, do not set ICC_VERSION or exportVersion. If exportVersion is set in your .cdsenv file, check that it is set as follows:

iccTranslator exportVersion int 11

Note: Several placement environment variables have equivalent variables to control the Virtuoso custom router. Placer variables always override their router equivalents during placement.

Setting MOS Chaining and Folding Parameters

You can set several.cdsenv parameters to control MOS device folding and chaining.

lxAllowPseudoParallelNets

Enables detection of pseudo-parallel nets (nets with only two devices connected and those devices are folded into the same number of fingers) if set tot. The default is nil.

Virtuoso XL Layout Editor User Guide

Using the Virtuoso Custom Placer

To see the significance of pseudo-parallel nets, consider a symmetric series of N-transistors, A and B, tied in a series pulldown chain to ground, as shown in the following figure.

Both A and B are folded into two legs, with A1, net_PP, and B1 connected in series to ground, and likewise A2 and B2 connected in series to ground, with both pairs in parallel. The nodes between A1 and B1 and between A2 and B2 are electrically equivalent. In reality no current passes through that connection and it need not physically be made.

The Assura™ ® verification tool understands pseudo-parallel connections and does not report incomplete nets in such situations.

lxStackPartitionParameters

Sets the device stacking partition parameters. The value is a list of two items. Use the values (-1 -1) to let Virtuoso XL decide how to handle each stack. The default values are (1 8).

The first value controls how far up in the hierarchy Virtuoso XL looks for opportunities to abut devices starting from the leaf node. A value of 1 permits abutment of devices within the same gate only. A value of 2 permits abutment of any devices with the same parent 2 levels from the leaf node. Higher values permit abutment with devices at progressively higher levels of the design hierarchy.