- •Contents
- •Preface
- •Related Documents
- •Typographic and Syntax Conventions
- •Introduction to the Virtuoso XL Layout Editor
- •Editing Your Technology File for Virtuoso XL Layout Editor
- •Sample Technology File
- •Virtuoso XL Technology File Requirements
- •Layer Rules
- •Devices
- •Physical Rules
- •Virtuoso XL Rules (lxRules)
- •Compactor Rules
- •Preparing Your Connectivity Source for the Virtuoso XL Layout Editor
- •Placing Design Elements
- •Using Design Variables
- •Netlist Processor Expressions
- •Analog Expression Language Expressions
- •Simulation Design Variables
- •Using One-to-Many Mapping
- •Iterated Instances and Bus Pins
- •Multiplication Factor (mfactor)
- •Series-Connection Factor (sfactor)
- •One-to-Many Assignment with the Update Device Correspondence
- •Using Many-to-Many or Many-to-One Mapping
- •Modifying Many-to-Many or Many-to-One Mapping Between Components
- •Deleting Many-to-Many or Many-to-One Mapping Between Components
- •Using Virtuoso XL Properties
- •Using the lxUseCell Property to Specify Layout Devices to Use
- •Using the lvsIgnore Property to Exclude Schematic Symbols
- •Using the lxlgnoredParams Property to Exclude Device Properties
- •Using the lxRemoveDevice property to Ignore Parasitic Devices
- •Using the lxViewList and lxStopList Properties to Prepare Hierarchical Designs
- •Using the lxCombination Property to Build Complex Devices
- •Preparing Instances and Pins in Your Layout for the Virtuoso XL Layout Editor
- •Preparing Pins for the Virtuoso XL Layout Editor
- •Preparing Pins for Permutability
- •Search Order Variable
- •Syntax
- •Macros
- •Setting the permuteRule Property in the Symbol Master
- •Setting the permuteRule Property in the Device Master
- •Setting the permuteRule Property in the Symbol Instance
- •Setting the permuteRule Property in the Device Instance
- •Setting the permuteRule Property in the Component Description Format
- •Preparing Instances for Hierarchical Connectivity Checking
- •Setting Up Your Desktop
- •Customizing Your Desktop Layout
- •Using Multiple Cellviews
- •Printing to the Command Interpreter Window
- •Changing Display Colors
- •Using Bindkeys
- •Displaying Bindkeys
- •Loading Virtuoso XL Bindkeys
- •Setting Environment Variables
- •Information About Online Forms
- •Layout XL Options Form
- •Introduction to Abutment
- •Abutment Requirements
- •Setting Up Cells for Abutment
- •abutAccessDir
- •abutClass
- •Steps in Auto-Abutment
- •Sample Parameterized Cells Set Up for Abutment
- •Example 1
- •Example 2
- •Creating CMOS Pcells to Use with Abutment
- •autoAbutment Properties
- •The abutMosStretchMat Property
- •abutMosStretchMat Rules for MOS Abutment
- •Example Code Setting MOS Abutment Properties
- •Setting Environment Variables for Abutment
- •Move Together
- •Constraint Assisted
- •Using Device Abutment
- •Generating Your Layout with Virtuoso XL Layout Editor
- •Starting Virtuoso XL from the Schematic
- •Importing a Netlist for a Connectivity Reference
- •Starting Virtuoso XL from the Layout View
- •Connectivity Reference as a Netlist
- •Mapping File Structure
- •Working with Template Files
- •Saving Form Contents
- •Loading Template Files
- •Modifying Templates
- •Loading Template Files
- •Creating Template Files
- •Template File Syntax
- •General Syntax Rules
- •Boundaries Section
- •I/O Pins Section
- •Sample Template
- •Generating a Layout with Components Not Placed (Gen From Source)
- •Moving Components from the Schematic into the Layout (Pick from Schematic)
- •Placing a Group of Schematic Elements Together
- •Placing Individual Components
- •Generating Pins
- •Viewing Unplaced Instances/Pins
- •Viewing in Place
- •Manually Abutting Devices Using Pick from Schematic
- •Cloning Components
- •Cloning
- •Troubleshooting
- •Cloning Using Multiple Cellviews
- •Using Correspondence Points
- •Information About Online Forms
- •Add Correspondence Pairs Form
- •Cloning Form
- •Correspondence Pairs Form
- •Import XL Netlist Form
- •Layout Generation Options Form
- •Open File Form
- •Pick from Schematic Form
- •Remove Correspondence Components Form
- •Set Pin Label Text Style Form
- •Startup Option Form
- •Template File Form
- •Editing Your Layout with Virtuoso XL Layout Editor
- •Identifying Incomplete Nets
- •Moving Objects Manually in the Virtuoso XL Layout Editor
- •Moving Objects Using Move Options
- •Setting the Move Form to Appear Automatically
- •Aligning Objects
- •Post Selecting Devices
- •PreSelecting Devices
- •Swapping Components
- •Permuting Component Pins
- •Permuting Pins Manually
- •Checking Permutation Information
- •Using Device Locking
- •Using Automatic Spacing
- •Using Interactive Device Abutment
- •Setting Component Types
- •About Component Types
- •MOS Transistor Stacking and Folding Parameters
- •Modifying a Component Type
- •Using Transistor Chaining
- •Using Transistor Folding
- •Controlling the Folding Grid
- •Folding Transistors
- •Adding Instances to a Layout
- •Adding Pins to a Layout
- •Assigning Pins to a Net
- •Maintaining Connectivity When Editing a Flattened Pcell
- •Information About Online Forms
- •Assign Nets Form
- •Edit Component Types Form
- •Move Form
- •Set Transistor Folding Form
- •Show Incomplete Nets Form
- •Stretch Form
- •Virtuoso XL Alignment Form
- •Using the Virtuoso Custom Placer
- •Overview
- •Main Features
- •Place Menu Command Summary
- •Other Commands Used with the Virtuoso custom placer
- •Placement Styles
- •Setting Up the Virtuoso XL Layout Editor for Placement
- •Identifying the Placement Translation Rules
- •Setting Cadence Design Framework II Environment Variables
- •Setting Environment Variables for the Virtuoso Custom Router and Placer
- •Setting MOS Chaining and Folding Parameters
- •Abutting Standard Cells
- •Using Auto-Abutment During Placement
- •Placement Constraints
- •Constraint Manager Geometric Constraints
- •Pin Placement Constraints
- •Constraint Limitations
- •Placement Parameters and Component Types
- •MOS Transistor Chaining and Folding Parameters
- •Pin Placement
- •Assigning Pins to an Edge
- •Assigning Pins to a Fixed Position
- •Railing Pins
- •Loading the Template File
- •Assigning Spacing Between Pins
- •Saving Pin Placement to a Template File
- •Partitioning the Design
- •Creating a Partition
- •Loading the Template File
- •Saving Partitions to a Template File
- •Setting Placement Planning
- •Assisted CMOS Placement
- •Choose Component Types Form
- •Running the Virtuoso Custom Placer
- •Prerequisites to Placement
- •Running the Virtuoso Custom Placer: Initial Placement
- •Stopping the Placer
- •Running Load Balancing Service (LBS)
- •Troubleshooting Placement Results
- •Running the Virtuoso Custom Placer: Detailed Placement
- •Showing Congestions
- •Information About Forms
- •Auto Placer Form
- •Partitioning Form
- •Choose Component Types Form
- •Pin Placement Form
- •Load Template File Form
- •Placement Planning Form (Assisted CMOS)
- •Placement Planning Form (Assisted Standard Cell)
- •Placement Planning Form (Assisted Mixed CMOS/Standard-Cell)
- •Preparing Your Design for Routing in the Virtuoso XL Layout Editor
- •Understanding Connectivity
- •Pseudo-Parallel Connections
- •Selecting Layers
- •Changing Layers
- •Connecting Nets
- •Creating Paths
- •Connecting Nets with Path Stitching
- •Connecting Nets with Design Shapes
- •Checking Connectivity with Flight Lines
- •Checking Connectivity with Markers
- •Finding Markers
- •Explaining Markers
- •Deleting Single Markers
- •Deleting All Markers
- •Using the Virtuoso Compactor on a Routed Design
- •Overview
- •Main Features
- •Wire Editing Commands
- •Virtuoso Custom Router to Virtuoso XL Command Mapping
- •Prerequisites
- •Rule Information
- •Net Connectivity Information
- •Routing Area Boundary
- •Enabling Wire Editing
- •Toggling Between Virtuoso XL and Wire Editing Enabled
- •Loading ASCII Rules Files
- •The Wire Editing Environment
- •Status Banner
- •Preview Wires and Routing Aids
- •Mouse Button Behavior
- •Using Environment Variables
- •Routing Paths
- •Routing a Single Path
- •Routing Multiple Paths
- •Preventing and Checking Design Rule Violations
- •Interactive Checking
- •Same Net Checking
- •Checking Regions
- •Checking Route and Pin Violations
- •Routing Options and Styles
- •Matching Path Width and Pin Widths
- •Matching Path Width and Pin Widths for Multiple Paths
- •Gathering Bus Wires
- •Spacing for Gathered Bus Wires
- •Overriding Bus Spacing
- •Rotating the Bus Cursor
- •Cycling the Control Wire
- •Allowing Redundant Wiring
- •Allowing Orthogonal Jogs
- •Route To Cursor
- •Allow Floating Nets
- •Connecting Multiple Component Pins
- •Pushing Routes and Components
- •Routing Shielded Nets
- •Routing Tandem Layer Pairs
- •Using Vias
- •Changing Layers and Adding Vias
- •Using Vias Patterns on Multiple Paths
- •Legal Via Sites
- •Rotating Vias
- •Pseudo Vias
- •Editing Routed Connections
- •Stretching Paths and Vias
- •Splitting and Stretching Paths
- •Copying Routes
- •Using Critic Wire
- •Compacting Paths Using Pull
- •Displaying Reports
- •Displaying Routing Status Reports
- •Displaying Network Reports
- •Displaying Component Reports
- •Displaying Net Reports
- •Creating Rules Reports
- •Search Reports
- •Saving Reports
- •Setting Constraints
- •Using the Virtuoso Constraint Manager
- •Using .do Files
- •About the Forms
- •Add Via Form
- •Check Routes Form
- •Create Path Form
- •Find File Form
- •Layout
- •Reports Form
- •Route Options Form
- •Save As Form
- •Search Form
- •Split Form
- •Via Pattern Pop-up
- •Reports
- •Route Status Report Window
- •Network Report Window
- •Instance Report Window
- •Net Report Window
- •Rules Report Window
- •Setting Environment Variables
- •Troubleshooting
- •Finding Design Elements (Probing)
- •Probing Hierarchical Designs
- •Removing Probes
- •Exiting the Probe Command
- •Showing the Options Form
- •Checking Shorts and Opens
- •Comparing Design Elements and Parameters (Checking against the Connectivity Source)
- •Information About Online Forms
- •Probe Options Form
- •Updating Design Data in Virtuoso XL
- •Updating Layout Parameters
- •Updating Schematic Parameters
- •Updating Device Correspondence
- •Creating Device Correspondence
- •Needed Mode
- •Computer Aided Mode
- •Updating the Connectivity Reference
- •Changing the Device (Instance) View
- •Information About Online Forms
- •Change Instance View Form
- •Create Device Correspondence
- •Problems with the Interface
- •Invalid Markers from Previous Software Versions
- •Options Form Does Not Appear
- •Virtuoso XL Performance Is Slow
- •Problems with Editing
- •Components Move Slowly
- •Extra Probes Appear
- •Layout Generation Options Form Does Not Keep Values from the Last Entry
- •Parameters Not Updated
- •Schematic Not Editable
- •Warning to Update Your Design Appears at Startup
- •Problems with Connectivity
- •Connections Not Made
- •Incomplete Nets Command Does Not Recognize Connected Pins and Nets
- •Markers for Nonexistent Overlaps and Shorts Appear
- •Path Ends Not Accepted
- •Placement and Routing Do Not Run
- •Virtuoso XL Does Not Recognize Physical Vias
- •Moving Software Executables To a New Location
- •Environment Variables
- •Virtuoso XL Layout Editor
- •alignApplySeparation
- •alignApplySpacings
- •alignDirection
- •alignLayer
- •alignMethod
- •alignSelectionMode
- •alignSeparation
- •allowRotation
- •autoAbutment
- •autoArrange
- •autoPermutePins
- •autoSpace
- •checkTimeStamps
- •ciwWindow
- •compTypeRefLibs
- •constraintAssistedMode
- •createBoundaryLabel
- •crossSelect
- •extractEnable
- •extractStopLevel
- •globalPlacement
- •ignoredParams
- •ignoreNames
- •incNetCycleHilite
- •incNetHiliteLayer
- •infoWindow
- •initAspectRatio
- •initAspectRatioOption
- •initBoundaryLayer
- •initCreateBoundary
- •initCreateInstances
- •initCreateMTM
- •initCreatePins
- •initDoFolding
- •initDoStacking
- •initEstimateArea
- •initGlobalNetPins
- •initIOLabelType
- •initIOPinLayer
- •initIOPinName
- •initPinHeight
- •initPinMultiplicity
- •initPinWidth
- •initPrBoundaryH
- •initPrBoundaryW
- •initSymbolicPins
- •initUtilization
- •layoutWindow
- •lswWindow
- •lxAllowPseudoParallelNets
- •lxDeltaWidth
- •lxFingeringNames
- •lxGenerationOrientation
- •lxGenerationTopLevelOnly
- •lxInitResetSource
- •lxStackMinimalFolding
- •lxStackPartitionParameters
- •lxWidthTolerance
- •maintainConnections
- •mfactorNames
- •mfactorSplit
- •moveAsGroup
- •openWindow
- •optimizePlacement
- •paramTolerance
- •pathProbe
- •pathPurposeList
- •pathSwitchLayer
- •pathSwitchPurpose
- •preserveTerminalContacts
- •probeCycleHilite
- •probeDevice
- •probeHiliteLayer
- •probeInfoInCIW
- •probeNet
- •probePin
- •rowGroundLayer
- •rowGroundName
- •rowGroundWidth
- •rowPowerLayer
- •rowPowerName
- •rowPowerWidth
- •rowSupplyPosition
- •rowSupplySpacing
- •rowMOSSupplyPattern
- •rowSTDAllowFlip
- •rowSTDSupplyPattern
- •rulesFile
- •runTime
- •saveAs
- •saveAsCellName
- •saveAsLibName
- •saveAsViewName
- •schematicWindow
- •setPPConn
- •sfactorNames
- •sfactorParam
- •showIncNetEnable
- •stopList
- •templateFileName
- •traverseMixedHierarchies
- •updateReplacesMasters
- •updateWithMarkers
- •vcpConductorDepth
- •vcpKeepoutDepth
- •viewList
- •Wire Editor
- •allowFloatingNets
- •allowJogs
- •allowRedundantWiring
- •autoAdjustLength
- •autoShield
- •busOverride
- •busOverrideValue
- •busWireSpacing
- •busWireSpacingType
- •checkCornerCorner
- •checkCrosstalk
- •checkLength
- •checkLimitWay
- •checkMaxProcessWireWidth
- •checkMaxStackViaDepth
- •checkMaxTotalVia
- •checkMinMaskEdgeLength
- •checkMinProcessWireWidth
- •checkMiter
- •checkNetOrder
- •checkOffManGridPin
- •checkOffWireGridPin
- •checkPinSpacing
- •checkPolygonWire
- •checkProtected
- •checkReentrantPath
- •checkRegion
- •checkSameNet
- •checkSegment
- •checkStub
- •checkUseLayers
- •checkUseVias
- •checkWireExtension
- •doFile
- •enableBusRouting
- •enableTandemPair
- •gatherBusWires
- •inaccessiblePin
- •interactiveChecking
- •matchPinWidth
- •matchPinWidthValue
- •matchWireWidth
- •multiplePinsConnection
- •pinLargerMaxProcessWidth
- •pinSmallerMinProcessWidth
- •pushComponent
- •pushRouting
- •routeAsManyAsPossible
- •routeToCursor
- •routeToCursorStyle
- •sameNetChecking
- •showTimingMeter
- •showTimingOctagon
- •snapToPinOrigin
- •useDoFile
- •useRulesFile
- •viaAssistance
- •viaPattern
- •Private Environment Variables
- •Virtuoso XL Command Quick Reference
- •Using Spice and CDL For Netlist Driven Layout Generation
- •Introduction
- •Specifying Spice Designs
- •Cell Creation Rules
- •Character Considerations
- •Spice Statements
- •File Level Statements
- •Statements Allowed at File Level or within a Subckt Cell or a Top Level Cell
- •Statements Allowed within a Subckt Cell or a Top Level Cell
- •Spice Design Example
- •CDL Design Example
- •Parameter Resolution
- •Parameter Levels
- •Resolving Parameters
- •Putting the Rules Together (Examples)
- •Parameter Scaling
- •Complete ibuf Example Results
- •Virtuoso XL .do File Commands
- •Rule Hierarchy
- •circuit
- •Syntax
- •Example
- •Syntax
- •Example
- •limit
- •Syntax
- •Example
- •rule
- •Syntax
- •Example
- •Syntax
Virtuoso XL Layout Editor User Guide
Using Spice and CDL For Netlist Driven Layout Generation
reference, Fet reference, Capacitor reference, or Resistor reference statements are instance level parameters.
Parameter levels are an important consideration for parameter resolution. This will be seen in the Resolving Parameters section.
Resolving Parameters
The VXL Spice Reader contains a resolver that resolves parameters to values. Resolution is based on a set of rules that take into account the value type of the parameter, the level of the parameter, and possibly the scale factor. Scaling will be discussed in the Scaling Parameters section.
Literal string parameters are fully resolved as specified. Numerical parameters are also resolved as specified, except that they may need to be scaled by a scale factor. Variable parameters are resolved by various rules that are described below.
Rule 1 : The first basic rule for variable parameter resolution is to look, at the next parameter level up, for the parameter of the variable name specified by the parameter being resolved.
For example, when attempting to resolve the parameter W which was specified asW = wpar, the resolver will look for the parameter wpar at the next parameter level up. So, for example, if wpar = 6U at the next higher level, then W will resolve to the value 6U.
Restriction : The implication of this rule is that the resolver will not look at the same level to resolve a parameter.
For example, if in the specification of a particular instance, the parametersW = wpar and wpar = 4U are specified, the resolver will not resolveW to the value 4U.
File level variable parameters are considered resolved to their variable (string) value, since there is nowhere else to look to try to resolve them. For example, at the file level, the parameter W = wpar, W will resolve to the string wpar.
Cell level variable parameters can be resolved only by using the file level parameters of the file in which the cell resides. If the variable parameter value cannot be found as a parameter at the file level, then the cell level parameter is considered resolved. For example, at the cell level, are the parameters W1 = wp1, W2 = wp2, and W3 = wp3 and, at the file level, are the parameterswp1 = 4U and wp2 = wstr. W1 will resolve to 4U, W2 will resolve to the string wstr, and W3 will resolve to the string wp3.
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The situation for instance level variable parameters is more complex than that of parameters at the file or cell level. This is because Spice and CDL allow parameters to be passed into an instance from the instance above it in the instance tree. Further, instance level parameters can be inherited from the master cell of the instance.
If a parameter exists on the master cell of an instance, but that parameter does exist on the instance itself, then the instance inherits that parameter from the master cell. For example, an instance does not contain the parameter W but the master cell for that instances specifies,W = 4U, then the instance inherits the W parameter and the value 4U is assigned to it.
Parameter passing plays a large role in variable parameter resolution for instances.
The resolver follows certain rules for parameter passing.
Rule 2 : Only parameters specified on the cell definition lineSUBCKT(. or .MODEL line) of the cell in which an instance resides, can be passed into an instance.
For example, for instance Xi1 of the cell named excel defined below,
.SUBCKT excel I O wp1 = 5U
.PARAM wp2 = 6U
Xi1 I A inv W1 = wp1 W2 = wp2
A value for wp1 may be passed into Xi1 but a value for wp2 cannot. This is because wp1 is specified on the.SUBKCT line but wp2 is not.
Rule 3 : The order of priority for variable parameter searching during resolution is
1.Parameters passed via instance.
2.Cell level parameters.
3.File level parameters.
4.Parameters from the master of the instance.
Putting the Rules Together (Examples)
The following Spice netlist example will be used to illustrate various cases of parameter resolution. Results for all possible instance tree combinations down to the fet level can be found in the Complete ibuf Example Results section.
File : IBUF.SP
.GLOBAL vdd gnd
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.option scale=1.0
.param PPP=600U W=400U L=400.5U P1=401U P2=402U P3=403U P4=404U P5=405U
.include '/net/mycds/spice_files/IBUF_I.SP'
.subckt IBUFTWO I O W=200U L=200.5U P1=201U P2=202U P4=204U
.param P3=203U PP3=213U *port input I
*port output O
Xinv1 I A MIV W=100U L=L P1=101U P2=102U P4=104U
Xinv2 A B MIV W=P1 WW=105U
Xinv3 B C MIV P5=PPP
Xinv4 C O MIV P1=W P4=WW
.ends
* top level *port input II *port output OO
Xibuf1 II AA IBUFTWO W=300U P1=P3
Xibuf2 AA BB IBUFTWO W=P1 L=P4
Xibuf3 BB OO IBUFTWO L=PP3
File : IBUF_I.SP
*
.GLOBAL vdd:P gnd:G
.option scale = 1.0
.param P4=20U P5=25U PP1=21U PP2=22U PP3=23U
.model TN nmos level=2 L=1.0U W=2.0U WW=3U PP4=34U
.model TP pmos W=2.5U L=1.5U level=2 WW=4U
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.subckt MIV A Q L=4.0U W=5.0U P1=6.0U P2=7.0U P3=8U P4=9U P5=PP1
.param WW=30U LL=31U PP3=32U
*port input A
*port output Q
m1 vdd A B vdd TP W=9e-07 L=1e-06
m2 B A gnd gnd TN 3.0U 2.0U
m3 vdd B C vdd TP W L
m4 C B gnd gnd TN W=P1 L=P2
m5 vdd C D vdd TP WW L=P3
m6 D C gnd gnd TN W=WW L=P4
m7 vdd D E vdd TP L=P5 W=PP2
m8 E D gnd gnd TN
m9 vdd E Q vdd TP W=WW L=LL
m10 Q E gnd gnd TN W=PP3 L=PP4
.ends
Ex 1 : InstTree = Xibuf1@IBUF / Xinv1@IBUFTWO / m1@MIV
Parameter = W
Value = 9e-7
Reason : W is set to the value 9e-7. Note that for all instance trees ending m1@MIV, will take on the value 9e-7.
Ex 2 : InstTree = Xibuf1@IBUF / Xinv1@IBUFTWO / m2@MIV
Parameter = L
Value = 2.0U
Reason : Fet m2, employs implied parameters. The first corresponds to W and the second to L. Here L set to 2.0U. For all instance trees ending at m2@MIV, L will take on the value 2.0U
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Ex 3 : InstTree = Xibuf1@IBUF / Xinv1@IBUFTWO / m4@MIV
Parameter = W
Value = 101U
Reason : Fet m4, specifies W = P1 Since P1 is specified on the .SUBCKT line of MIV, it can be passed into m4. Xinv1, the instance above m4, in the instance specifies P1 = 101U.
Ex 4 : InstTree = Xibuf1@IBUF / Xinv1@IBUFTWO / m3@MIV
Parameter = W
Value = 100U
Reason : Fet m3, employs implied parameters. The first corresponds to W, resulting in W = W. Since W is specified on the .SUBCKT line of MIV, it can be passed into m3. Xinv1 specifies W = 100U.
Ex 5 : InstTree = Xibuf1@IBUF / Xinv1@IBUFTWO / m5@MIV
Parameter = L
Value = 8U
Reason : Fet m5, specifies L = P3. Since P3 is specified on the .SUBCKT line of MIV, it can be passed into m5. However, Xinv1 doesn’t specify P3. So the value for P3 is 8U, being obtained from the cell level specification in MIV.
Ex 6 : InstTree = Xibuf1@IBUF / Xinv2@IBUFTWO / m6@MIV
Parameter = W
Value = 30U
Reason : Fet m5 specifies W = WW. Since WW is not specified on the .SUBCKT line of MIV, it cannot be passed into m6. So the value for WW is 30U, being obtained from the cell level specification in MIV.
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Ex 7 : InstTree = Xibuf1@IBUF / Xinv4@IBUFTWO / m4@MIV
Parameter = W
Value = 300U
Reason : Fet m4 specifies W = P1. Since P1 is on the .SUBCKT line of MIV, it can be passed in from Xinv4. Xinv4 specifies P1 = W. Since W is on the .SUBCKT line of IBUFTWO, it can be passed into xinv4. Xibuf1 specifies W = 300U.
Ex 8 : InstTree = Xibuf2@IBUF / Xinv3@IBUFTWO / m7@MIV
Parameter = L
Value = 600U
Reason : Fet m7 specifies L = P5. P5 can be passed into m7. Xinv3 specifies P5 = PPP. PPP cannot be passed into Xinv3. Further, PPP is not at the cell level for Xinv3 because it was not specified on the .SUBCKT IBUF2 nor in the .PARAM statement inside IBUFTWO. However, PPP can be found at the file level for Xinv3, being specified on the .PARAM statement of the file in which Xinv3 resides. Thus PPP = 600U.
Ex 9 : InstTree = Xibuf1@IBUF / Xinv4@IBUFTWO / m10@MIV
Parameter = L
Value = 34U
Reason : Fet m10 specifies L = PP4. PP4 cannot be passed into m10. PP4 is not at the cell level for m10. PP4 is also not at the file level for m10. It is, however, at the master level,being specified as PP4 = 34U, on the parameter list for model TN.
Ex 10 : InstTree = Xibuf1@IBUF / Xinv4@IBUFTWO / m8@MIV
Parameter = W
Value = 2.0U
Reason : Fet m10 does not specifies. However, its master, TN, specifies W = 2.0U. Fet m10 inherits this value.
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