- •Contents
- •Preface
- •Related Documents
- •Typographic and Syntax Conventions
- •Introduction to the Virtuoso XL Layout Editor
- •Editing Your Technology File for Virtuoso XL Layout Editor
- •Sample Technology File
- •Virtuoso XL Technology File Requirements
- •Layer Rules
- •Devices
- •Physical Rules
- •Virtuoso XL Rules (lxRules)
- •Compactor Rules
- •Preparing Your Connectivity Source for the Virtuoso XL Layout Editor
- •Placing Design Elements
- •Using Design Variables
- •Netlist Processor Expressions
- •Analog Expression Language Expressions
- •Simulation Design Variables
- •Using One-to-Many Mapping
- •Iterated Instances and Bus Pins
- •Multiplication Factor (mfactor)
- •Series-Connection Factor (sfactor)
- •One-to-Many Assignment with the Update Device Correspondence
- •Using Many-to-Many or Many-to-One Mapping
- •Modifying Many-to-Many or Many-to-One Mapping Between Components
- •Deleting Many-to-Many or Many-to-One Mapping Between Components
- •Using Virtuoso XL Properties
- •Using the lxUseCell Property to Specify Layout Devices to Use
- •Using the lvsIgnore Property to Exclude Schematic Symbols
- •Using the lxlgnoredParams Property to Exclude Device Properties
- •Using the lxRemoveDevice property to Ignore Parasitic Devices
- •Using the lxViewList and lxStopList Properties to Prepare Hierarchical Designs
- •Using the lxCombination Property to Build Complex Devices
- •Preparing Instances and Pins in Your Layout for the Virtuoso XL Layout Editor
- •Preparing Pins for the Virtuoso XL Layout Editor
- •Preparing Pins for Permutability
- •Search Order Variable
- •Syntax
- •Macros
- •Setting the permuteRule Property in the Symbol Master
- •Setting the permuteRule Property in the Device Master
- •Setting the permuteRule Property in the Symbol Instance
- •Setting the permuteRule Property in the Device Instance
- •Setting the permuteRule Property in the Component Description Format
- •Preparing Instances for Hierarchical Connectivity Checking
- •Setting Up Your Desktop
- •Customizing Your Desktop Layout
- •Using Multiple Cellviews
- •Printing to the Command Interpreter Window
- •Changing Display Colors
- •Using Bindkeys
- •Displaying Bindkeys
- •Loading Virtuoso XL Bindkeys
- •Setting Environment Variables
- •Information About Online Forms
- •Layout XL Options Form
- •Introduction to Abutment
- •Abutment Requirements
- •Setting Up Cells for Abutment
- •abutAccessDir
- •abutClass
- •Steps in Auto-Abutment
- •Sample Parameterized Cells Set Up for Abutment
- •Example 1
- •Example 2
- •Creating CMOS Pcells to Use with Abutment
- •autoAbutment Properties
- •The abutMosStretchMat Property
- •abutMosStretchMat Rules for MOS Abutment
- •Example Code Setting MOS Abutment Properties
- •Setting Environment Variables for Abutment
- •Move Together
- •Constraint Assisted
- •Using Device Abutment
- •Generating Your Layout with Virtuoso XL Layout Editor
- •Starting Virtuoso XL from the Schematic
- •Importing a Netlist for a Connectivity Reference
- •Starting Virtuoso XL from the Layout View
- •Connectivity Reference as a Netlist
- •Mapping File Structure
- •Working with Template Files
- •Saving Form Contents
- •Loading Template Files
- •Modifying Templates
- •Loading Template Files
- •Creating Template Files
- •Template File Syntax
- •General Syntax Rules
- •Boundaries Section
- •I/O Pins Section
- •Sample Template
- •Generating a Layout with Components Not Placed (Gen From Source)
- •Moving Components from the Schematic into the Layout (Pick from Schematic)
- •Placing a Group of Schematic Elements Together
- •Placing Individual Components
- •Generating Pins
- •Viewing Unplaced Instances/Pins
- •Viewing in Place
- •Manually Abutting Devices Using Pick from Schematic
- •Cloning Components
- •Cloning
- •Troubleshooting
- •Cloning Using Multiple Cellviews
- •Using Correspondence Points
- •Information About Online Forms
- •Add Correspondence Pairs Form
- •Cloning Form
- •Correspondence Pairs Form
- •Import XL Netlist Form
- •Layout Generation Options Form
- •Open File Form
- •Pick from Schematic Form
- •Remove Correspondence Components Form
- •Set Pin Label Text Style Form
- •Startup Option Form
- •Template File Form
- •Editing Your Layout with Virtuoso XL Layout Editor
- •Identifying Incomplete Nets
- •Moving Objects Manually in the Virtuoso XL Layout Editor
- •Moving Objects Using Move Options
- •Setting the Move Form to Appear Automatically
- •Aligning Objects
- •Post Selecting Devices
- •PreSelecting Devices
- •Swapping Components
- •Permuting Component Pins
- •Permuting Pins Manually
- •Checking Permutation Information
- •Using Device Locking
- •Using Automatic Spacing
- •Using Interactive Device Abutment
- •Setting Component Types
- •About Component Types
- •MOS Transistor Stacking and Folding Parameters
- •Modifying a Component Type
- •Using Transistor Chaining
- •Using Transistor Folding
- •Controlling the Folding Grid
- •Folding Transistors
- •Adding Instances to a Layout
- •Adding Pins to a Layout
- •Assigning Pins to a Net
- •Maintaining Connectivity When Editing a Flattened Pcell
- •Information About Online Forms
- •Assign Nets Form
- •Edit Component Types Form
- •Move Form
- •Set Transistor Folding Form
- •Show Incomplete Nets Form
- •Stretch Form
- •Virtuoso XL Alignment Form
- •Using the Virtuoso Custom Placer
- •Overview
- •Main Features
- •Place Menu Command Summary
- •Other Commands Used with the Virtuoso custom placer
- •Placement Styles
- •Setting Up the Virtuoso XL Layout Editor for Placement
- •Identifying the Placement Translation Rules
- •Setting Cadence Design Framework II Environment Variables
- •Setting Environment Variables for the Virtuoso Custom Router and Placer
- •Setting MOS Chaining and Folding Parameters
- •Abutting Standard Cells
- •Using Auto-Abutment During Placement
- •Placement Constraints
- •Constraint Manager Geometric Constraints
- •Pin Placement Constraints
- •Constraint Limitations
- •Placement Parameters and Component Types
- •MOS Transistor Chaining and Folding Parameters
- •Pin Placement
- •Assigning Pins to an Edge
- •Assigning Pins to a Fixed Position
- •Railing Pins
- •Loading the Template File
- •Assigning Spacing Between Pins
- •Saving Pin Placement to a Template File
- •Partitioning the Design
- •Creating a Partition
- •Loading the Template File
- •Saving Partitions to a Template File
- •Setting Placement Planning
- •Assisted CMOS Placement
- •Choose Component Types Form
- •Running the Virtuoso Custom Placer
- •Prerequisites to Placement
- •Running the Virtuoso Custom Placer: Initial Placement
- •Stopping the Placer
- •Running Load Balancing Service (LBS)
- •Troubleshooting Placement Results
- •Running the Virtuoso Custom Placer: Detailed Placement
- •Showing Congestions
- •Information About Forms
- •Auto Placer Form
- •Partitioning Form
- •Choose Component Types Form
- •Pin Placement Form
- •Load Template File Form
- •Placement Planning Form (Assisted CMOS)
- •Placement Planning Form (Assisted Standard Cell)
- •Placement Planning Form (Assisted Mixed CMOS/Standard-Cell)
- •Preparing Your Design for Routing in the Virtuoso XL Layout Editor
- •Understanding Connectivity
- •Pseudo-Parallel Connections
- •Selecting Layers
- •Changing Layers
- •Connecting Nets
- •Creating Paths
- •Connecting Nets with Path Stitching
- •Connecting Nets with Design Shapes
- •Checking Connectivity with Flight Lines
- •Checking Connectivity with Markers
- •Finding Markers
- •Explaining Markers
- •Deleting Single Markers
- •Deleting All Markers
- •Using the Virtuoso Compactor on a Routed Design
- •Overview
- •Main Features
- •Wire Editing Commands
- •Virtuoso Custom Router to Virtuoso XL Command Mapping
- •Prerequisites
- •Rule Information
- •Net Connectivity Information
- •Routing Area Boundary
- •Enabling Wire Editing
- •Toggling Between Virtuoso XL and Wire Editing Enabled
- •Loading ASCII Rules Files
- •The Wire Editing Environment
- •Status Banner
- •Preview Wires and Routing Aids
- •Mouse Button Behavior
- •Using Environment Variables
- •Routing Paths
- •Routing a Single Path
- •Routing Multiple Paths
- •Preventing and Checking Design Rule Violations
- •Interactive Checking
- •Same Net Checking
- •Checking Regions
- •Checking Route and Pin Violations
- •Routing Options and Styles
- •Matching Path Width and Pin Widths
- •Matching Path Width and Pin Widths for Multiple Paths
- •Gathering Bus Wires
- •Spacing for Gathered Bus Wires
- •Overriding Bus Spacing
- •Rotating the Bus Cursor
- •Cycling the Control Wire
- •Allowing Redundant Wiring
- •Allowing Orthogonal Jogs
- •Route To Cursor
- •Allow Floating Nets
- •Connecting Multiple Component Pins
- •Pushing Routes and Components
- •Routing Shielded Nets
- •Routing Tandem Layer Pairs
- •Using Vias
- •Changing Layers and Adding Vias
- •Using Vias Patterns on Multiple Paths
- •Legal Via Sites
- •Rotating Vias
- •Pseudo Vias
- •Editing Routed Connections
- •Stretching Paths and Vias
- •Splitting and Stretching Paths
- •Copying Routes
- •Using Critic Wire
- •Compacting Paths Using Pull
- •Displaying Reports
- •Displaying Routing Status Reports
- •Displaying Network Reports
- •Displaying Component Reports
- •Displaying Net Reports
- •Creating Rules Reports
- •Search Reports
- •Saving Reports
- •Setting Constraints
- •Using the Virtuoso Constraint Manager
- •Using .do Files
- •About the Forms
- •Add Via Form
- •Check Routes Form
- •Create Path Form
- •Find File Form
- •Layout
- •Reports Form
- •Route Options Form
- •Save As Form
- •Search Form
- •Split Form
- •Via Pattern Pop-up
- •Reports
- •Route Status Report Window
- •Network Report Window
- •Instance Report Window
- •Net Report Window
- •Rules Report Window
- •Setting Environment Variables
- •Troubleshooting
- •Finding Design Elements (Probing)
- •Probing Hierarchical Designs
- •Removing Probes
- •Exiting the Probe Command
- •Showing the Options Form
- •Checking Shorts and Opens
- •Comparing Design Elements and Parameters (Checking against the Connectivity Source)
- •Information About Online Forms
- •Probe Options Form
- •Updating Design Data in Virtuoso XL
- •Updating Layout Parameters
- •Updating Schematic Parameters
- •Updating Device Correspondence
- •Creating Device Correspondence
- •Needed Mode
- •Computer Aided Mode
- •Updating the Connectivity Reference
- •Changing the Device (Instance) View
- •Information About Online Forms
- •Change Instance View Form
- •Create Device Correspondence
- •Problems with the Interface
- •Invalid Markers from Previous Software Versions
- •Options Form Does Not Appear
- •Virtuoso XL Performance Is Slow
- •Problems with Editing
- •Components Move Slowly
- •Extra Probes Appear
- •Layout Generation Options Form Does Not Keep Values from the Last Entry
- •Parameters Not Updated
- •Schematic Not Editable
- •Warning to Update Your Design Appears at Startup
- •Problems with Connectivity
- •Connections Not Made
- •Incomplete Nets Command Does Not Recognize Connected Pins and Nets
- •Markers for Nonexistent Overlaps and Shorts Appear
- •Path Ends Not Accepted
- •Placement and Routing Do Not Run
- •Virtuoso XL Does Not Recognize Physical Vias
- •Moving Software Executables To a New Location
- •Environment Variables
- •Virtuoso XL Layout Editor
- •alignApplySeparation
- •alignApplySpacings
- •alignDirection
- •alignLayer
- •alignMethod
- •alignSelectionMode
- •alignSeparation
- •allowRotation
- •autoAbutment
- •autoArrange
- •autoPermutePins
- •autoSpace
- •checkTimeStamps
- •ciwWindow
- •compTypeRefLibs
- •constraintAssistedMode
- •createBoundaryLabel
- •crossSelect
- •extractEnable
- •extractStopLevel
- •globalPlacement
- •ignoredParams
- •ignoreNames
- •incNetCycleHilite
- •incNetHiliteLayer
- •infoWindow
- •initAspectRatio
- •initAspectRatioOption
- •initBoundaryLayer
- •initCreateBoundary
- •initCreateInstances
- •initCreateMTM
- •initCreatePins
- •initDoFolding
- •initDoStacking
- •initEstimateArea
- •initGlobalNetPins
- •initIOLabelType
- •initIOPinLayer
- •initIOPinName
- •initPinHeight
- •initPinMultiplicity
- •initPinWidth
- •initPrBoundaryH
- •initPrBoundaryW
- •initSymbolicPins
- •initUtilization
- •layoutWindow
- •lswWindow
- •lxAllowPseudoParallelNets
- •lxDeltaWidth
- •lxFingeringNames
- •lxGenerationOrientation
- •lxGenerationTopLevelOnly
- •lxInitResetSource
- •lxStackMinimalFolding
- •lxStackPartitionParameters
- •lxWidthTolerance
- •maintainConnections
- •mfactorNames
- •mfactorSplit
- •moveAsGroup
- •openWindow
- •optimizePlacement
- •paramTolerance
- •pathProbe
- •pathPurposeList
- •pathSwitchLayer
- •pathSwitchPurpose
- •preserveTerminalContacts
- •probeCycleHilite
- •probeDevice
- •probeHiliteLayer
- •probeInfoInCIW
- •probeNet
- •probePin
- •rowGroundLayer
- •rowGroundName
- •rowGroundWidth
- •rowPowerLayer
- •rowPowerName
- •rowPowerWidth
- •rowSupplyPosition
- •rowSupplySpacing
- •rowMOSSupplyPattern
- •rowSTDAllowFlip
- •rowSTDSupplyPattern
- •rulesFile
- •runTime
- •saveAs
- •saveAsCellName
- •saveAsLibName
- •saveAsViewName
- •schematicWindow
- •setPPConn
- •sfactorNames
- •sfactorParam
- •showIncNetEnable
- •stopList
- •templateFileName
- •traverseMixedHierarchies
- •updateReplacesMasters
- •updateWithMarkers
- •vcpConductorDepth
- •vcpKeepoutDepth
- •viewList
- •Wire Editor
- •allowFloatingNets
- •allowJogs
- •allowRedundantWiring
- •autoAdjustLength
- •autoShield
- •busOverride
- •busOverrideValue
- •busWireSpacing
- •busWireSpacingType
- •checkCornerCorner
- •checkCrosstalk
- •checkLength
- •checkLimitWay
- •checkMaxProcessWireWidth
- •checkMaxStackViaDepth
- •checkMaxTotalVia
- •checkMinMaskEdgeLength
- •checkMinProcessWireWidth
- •checkMiter
- •checkNetOrder
- •checkOffManGridPin
- •checkOffWireGridPin
- •checkPinSpacing
- •checkPolygonWire
- •checkProtected
- •checkReentrantPath
- •checkRegion
- •checkSameNet
- •checkSegment
- •checkStub
- •checkUseLayers
- •checkUseVias
- •checkWireExtension
- •doFile
- •enableBusRouting
- •enableTandemPair
- •gatherBusWires
- •inaccessiblePin
- •interactiveChecking
- •matchPinWidth
- •matchPinWidthValue
- •matchWireWidth
- •multiplePinsConnection
- •pinLargerMaxProcessWidth
- •pinSmallerMinProcessWidth
- •pushComponent
- •pushRouting
- •routeAsManyAsPossible
- •routeToCursor
- •routeToCursorStyle
- •sameNetChecking
- •showTimingMeter
- •showTimingOctagon
- •snapToPinOrigin
- •useDoFile
- •useRulesFile
- •viaAssistance
- •viaPattern
- •Private Environment Variables
- •Virtuoso XL Command Quick Reference
- •Using Spice and CDL For Netlist Driven Layout Generation
- •Introduction
- •Specifying Spice Designs
- •Cell Creation Rules
- •Character Considerations
- •Spice Statements
- •File Level Statements
- •Statements Allowed at File Level or within a Subckt Cell or a Top Level Cell
- •Statements Allowed within a Subckt Cell or a Top Level Cell
- •Spice Design Example
- •CDL Design Example
- •Parameter Resolution
- •Parameter Levels
- •Resolving Parameters
- •Putting the Rules Together (Examples)
- •Parameter Scaling
- •Complete ibuf Example Results
- •Virtuoso XL .do File Commands
- •Rule Hierarchy
- •circuit
- •Syntax
- •Example
- •Syntax
- •Example
- •limit
- •Syntax
- •Example
- •rule
- •Syntax
- •Example
- •Syntax
Virtuoso XL Layout Editor User Guide
Generating Your Layout with Virtuoso XL Layout Editor
Information About Online Forms
■Add Correspondence Pairs Form on page 193
■Cloning Form on page 193
■Correspondence Pairs Form on page 195
■Define Connectivity Reference Form on page 195
■Display Specifi Correspondence Components Form on page 196
■Import XL Netlist Form on page 196
■Layout Generation Options Form on page 196
■Open File Form on page 200
■Pick from Schematic Form on page 200
■Remove Correspondence Components Form on page 203
■Set Pin Label Text Style Form on page 203
■Startup Option Form on page 204
Add Correspondence Pairs Form
Name in Connectivity Source lets you type the name of the connectivity point you want to be the source when you click Apply.
Name in Connectivity Target lets you type the name of the connectivity point you want to be the target when you click Apply.
Set By Cursor lets you indicate by clicking on a point with the cursor the name of the point you want added when you click Apply.
Cloning Form
Options
Draglines enables rubberbanding lines showing the closest possible connections to nets.
Correspondence File activates the Correspondence File field, to let you type in a name for a correspondence file, if you do not want to use the default name,lvs_corr_file.
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Create opens the Correspondence Pairs form, which lets you add correspondence points.
Target Schematic contains the circu8it which will be implemented by the clone command.
The default value for this field is the source from the cellview pair which launched the clone command.
Target Layout is the cellview where the clone will be placed. The default value for this field is the layout from which the clone command was invoked.
Find Matching Targets
Find Matching Targets on:
Entire Target Schematic performs a global search on the entire schematic to find matching objects.
Selected Set on Target Schematic performs a global search to find matching objects within the selected set.
Find Matching Targets using:
Permutation is allowed when searching for the matched components.
Exact Match requires isomorphism, instance masters, instance parameters for all matches between connectivity sources and connectivity targets.
Find Matching Targets invokes the pattern matching
Unplaced lists all components or structures that were chosen as target structures for cloning.
Placed lists all targets that have been cloned and placed in the target layout window.
Clone lets you indicate by clicking in the schematic or layout the component or structures that you want to be the targets for cloning.
Rotate rotates the component or structure to be placed 90 degrees counterclockwise.
Flip Horizontal mirrors the component or structure to be placed on the Y axis (flips it horizontally).
Flip Vertical mirrors the component or structure to be placed on the X axis (flips it vertically).
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Correspondence Pairs Form
Working File lets you accept the default name of the Correspondence Points File
(lvs_corr_file) or type a different name.
Add opens a form that lets you add correspondence points to the Correspondence Points
File.
Remove opens form that lets you delete correspondence points from the Correspondence Points File.
Display opens a form that lets you display individual correspondence points from the
Correspondence Points File.
Display All Pts opens a list box that shows all the correspondence points in the
Correspondence Points File.
Clear All Pts clears all correspondence points from the Correspondence Points File.
Define Connectivity Reference Form
Source specifies the connectivity source for the design.
Schematic indicates that a schematic is the connectivity reference for the design.
Netlist indicates that a netlist is the connectivity reference for the design.
None indicates that there is no connectivity reference for the design.
Library defaults to the name of the library in which the layout was opened. You can type in a different library name.
Cell lets you type in the name of the cell you want to use as a connectivity reference.
View defaults to schematic. You can type in a different view name.
Browse displays the Library Browser, which lets you click on names to fill in the form. Even if the Library Browser is already open, you must click Browse if you want the names you click on to appear in the form.
Sel by Cursor lets you specify the schematic or layout to use by clicking in the open cellview window.
Top Cell (appears only if you choose Netlist as the source) lets you enter the top cell of the netlist.
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Display Specific Correspondence Components Form
Identify Connectivity
Source sets the software to display the connectivity point identified as the source when you click Apply.
Target sets the software to display the connectivity point identified as the target when you click Apply
Name Of Point lets you type the name of the point you want displayed when you click Apply.
Set By Cursor lets you indicate by clicking on a point with the cursor the name of the point you want displayed when you click Apply.
Import XL Netlist Form
Netlist File specifies the name of the file to use as a netlist.
Copy copies the imported netlist file to the destination library location.
Link links the imported netlist file to the destination library location.
Move moves the imported netlist file to the destination library location.
Library specifies the name of the library in which you want to put the netlist.
Cell specifies the name of the cell in which you want to put the netlist.
View specifies the view name in which you want to store the netlist.
Browse opens the Open File form if your cursor is in the Netlist File text field. From the Open File form, you can choose any file to which you have access. If your cursor is in the Library or Cell or View fields, theBrowse button opens the Library Browser form, from which you can choose a library, cell, and view.
Format is either CDL or SPICE.
Check allows you to check the netlist for any errors before generating your layout. Any errors will be displayed in the CIW, along with a message stating that there are syntax errors which may be the result of unsupported syntaxes.
Layout Generation Options Form
Layout Generation
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Generate:
I/O Pins places all the pins specified in the Layout Generation Options form.
Instances places all the instances in the schematic that do not have Ignore properties attached to them.
Boundary generates a design boundary using the layer and size information you specify in the Boundary section of this form.
Transistor Chaining enables the abutment of ordered lists of MOS transistors into stacks and places them in the design.
Transistor Folding allows you to split devices into fingers which keeps the gate width from going beyond the manufacturing foundry specification size.
Preserve Mappings, if turned off, ignores previous many-to-many, many-to-one, and one-to-many mappings.
I/O Pins
Apply applies to all pins the default values to all of the pins displayed in the list box.
Pin Type lets you specify the type of pins to be placed.
Geometric specifies the layer on which you want to place the pins from theLayer/ Master cyclic field below.
Symbolic lets you choose the name of a symbolic pin cell from the Layer/Master cyclic field. If there are no symbolic pins defined in the technology file, this option is not available. If you choose this option, the Width field disappears (because symbolic pins are square).
Layer/Master lets you choose the layer for geometric pins.
The default is the current drawing layer if it is defined aslxExtractLayer in the technology file. Otherwise, the default is the first layer definedlxExtractLayeras , and the cyclic field offers only the conducting layers. If no layers have been defined as lxExtractLayer, the cyclic field shows all valid layout layers. The master displays the symbolic pins defined in the technology file. If none are shown in the cyclic field then there are no symbolic pins defined in the technology file.
Width specifies the width for each pin. The default is theminWidth property value set for the current layer in your technology file.
Height specifies the height for each pin. The default is theminWidth property value set for the current layer in your technology file.
Num specifies how many instances of this pin to create. If you type 0 in this field, the pin is not created.
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Create, when on, specifies which of the pins listed on the form (based on pins shown in the schematic) are to be placed on the layout.
Select allows you to type in a pin name and the pin will be selected in the list box.
Number Selected displays the number of pins that have been selected from the Select field.
Add a Pin adds a pin to the list box and to the layout after you click OK.
Update changes the Pin Type, Layer/Master, Width, Height, Num, and Create for one or more selected pins. To select more than one pin use the Control left mouse button.
Pin Type lets you specify the type of pins to be placed.
Geometric specifies the layer on which you want to place the pins from theLayer/
Master cyclic field below.
Symbolic lets you choose the name of a symbolic pin cell from the Layer/Master cyclic field. If there are no symbolic pins defined in the technology file, this option is not available. If you choose this option, the Width field disappears (because symbolic pins are square).
Layer/Master lets you choose
■The layer for geometric pins.
The default is the current drawing layer if it is defined aslxExtractLayer in the technology file. Otherwise, the default is the first layer definedlxExtractLayeras , and the cyclic field offers only the conducting layers. If no layers have been defined as lxExtractLayer, the cyclic field shows all valid layout layers.
■The master for symbolic pins.
If there are no valid symbolic pins defined in the technology file, none are shown in the cyclic field and theSymbolic Pin Type option is not available.
Width specifies the width for each pin. The default is theminWidth property value set for the current layer in your technology file.
Height specifies the height for each pin. The default is theminWidth property value set for the current layer in your technology file.
Num specifies how many instances of this pin to create. If you type0 in this field, the pin is not created.
Create, when on, specifies which of the pins listed on the form (based on pins shown in the schematic) are to be placed on the layout.
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Create Pin Labels puts the names of the pins on the layout.
Display Pin Name Option opens the Set Pin Label Text Style form, which allows you to set the size, font, style, justification, and orientation of the label lettering and the drawing or pin layer on which the labels are shown.
Pin Label Shape
Label creates a label on the layer specified on the Set Pin Label Text Style form.
Text creates text on the layer specified on the Set Pin Label Text Style form. If the text is not visible turn on the Pin Names option in the Display Options form.
None does not create a label or text for the pins.
Pin Label Options opens the Set Pin Label Text Style form, which allows you to set the size, font, style, justification and orientation of the label lettering and the drawing or pin layer on which the labels are shown.
Boundary
Layer specifies the layer on which you draw the cell boundary. The default is the entry layer defined by theinitBoundaryLayer environment variable. The default is the boundary entry layer.
Shape lets you set the shape to Rectangle or Polygon.
If you set Shape to Rectangle, you can set any two of the following values to define the size of the cell boundary.
Utilization (%) specifies the percentage of area within the cell boundary that you want to fill. The default is25%.
Boundary Width specifies the width of the design boundary. The default is the size of the last boundary or 10.
Boundary Height specifies the height of the design boundary. The default is the size of the last boundary or 10.
Aspect Ratio W/H is the width-to-height ratio of the design boundary. For example, a value of 1 specifies a square boundary, 0.5 specifies a boundary twice as high as it is wide, and 2 specifies a boundary twice as wide as it is high. The default is1.
Boundary Width specifies the width of the design boundary. The default is the size of the last boundary or 10.
Boundary Height specifies the height of the design boundary. The default is the size of the last boundary or 10.
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