Virtuoso XL Layout Editor User Guide

4

Preparing Instances and Pins in Your Layout for the Virtuoso XL Layout Editor

This chapter explains how to prepare layout elements for use with the Virtuoso® XL layout editor (Virtuoso XL). This chapter covers the following topics:

■Preparing Pins for the Virtuoso XL Layout Editor on page 74

■Preparing Pins for Permutability on page 75

■Preparing Instances for Hierarchical Connectivity Checking on page 96

You can also define pins to beconnected externally to the design.

Note: The layout window Connectivity commands let you tell the software to connect pins in four different ways:

Define Pins – Must Connect lets you connect selected pins in a net externally at a higher level of the hierarchy.

Define Pins – Strongly Connected lets you connect selected pins within the device. By default, pins are connected internally (strongly).

Define Pins – Weakly Connected lets you connect selected pins in a limited external connection to avoid specific internal connections (typically ones with high-resistance paths). lxHiSetOptions

Define Pins - Pseudo Parallel Connect lets you connect selected instance terminals on the same net within an instance as though they were connected externally; that is, they are defined as a connection but do not ever need to be physically connected.

For more information about must-connect pins, strongly connected pins, weakly connected pins, and pseudo-parallel connected pins, see “Defining Pin Connections” in Chapter 13 of the Virtuoso Layout Editor User Guide.

If you are using parameterized cells (pcells) and want to give them the capability for abutment

(overlapping pins to create a connection), see Chapter 6, “Setting Up Device Abutment.”

Virtuoso XL Layout Editor User Guide

Preparing Instances and Pins in Your Layout for the Virtuoso XL Layout Editor

Preparing Pins for the Virtuoso XL Layout Editor

For connectivity assignment tracing and cross-probing to work correctly in Virtuoso XL, the pins and pin names in the layout cellview of a device must match those in the corresponding schematic symbol.

If there are extra pins in the symbol, Virtuoso XL does not maintain their connectivity in the layout. If you add extra pins, whose names are global nets (for example, vdd!) to the layout, Virtuoso XL does maintain connectivity of these pins in the layout.

In addition, Virtuoso XL maintains connectivity of extra pins in the layout whose connectivity is defined viainherited connections. The inherited connection can be defined relative to the layout instance itself or relative to the schematic hierarchy that ends with the schematic instance corresponding to that layout instance.

Note: Do not place pins where you do not want to make a connection; for example, on a poly layer that covers the gate area of a FET.

If there are pins in the schematic that you do not want to show up in the layout, you can assign the ignoreNamesproperty to it.