- •Contents
- •Preface
- •Related Documents
- •Typographic and Syntax Conventions
- •Introduction to the Virtuoso XL Layout Editor
- •Editing Your Technology File for Virtuoso XL Layout Editor
- •Sample Technology File
- •Virtuoso XL Technology File Requirements
- •Layer Rules
- •Devices
- •Physical Rules
- •Virtuoso XL Rules (lxRules)
- •Compactor Rules
- •Preparing Your Connectivity Source for the Virtuoso XL Layout Editor
- •Placing Design Elements
- •Using Design Variables
- •Netlist Processor Expressions
- •Analog Expression Language Expressions
- •Simulation Design Variables
- •Using One-to-Many Mapping
- •Iterated Instances and Bus Pins
- •Multiplication Factor (mfactor)
- •Series-Connection Factor (sfactor)
- •One-to-Many Assignment with the Update Device Correspondence
- •Using Many-to-Many or Many-to-One Mapping
- •Modifying Many-to-Many or Many-to-One Mapping Between Components
- •Deleting Many-to-Many or Many-to-One Mapping Between Components
- •Using Virtuoso XL Properties
- •Using the lxUseCell Property to Specify Layout Devices to Use
- •Using the lvsIgnore Property to Exclude Schematic Symbols
- •Using the lxlgnoredParams Property to Exclude Device Properties
- •Using the lxRemoveDevice property to Ignore Parasitic Devices
- •Using the lxViewList and lxStopList Properties to Prepare Hierarchical Designs
- •Using the lxCombination Property to Build Complex Devices
- •Preparing Instances and Pins in Your Layout for the Virtuoso XL Layout Editor
- •Preparing Pins for the Virtuoso XL Layout Editor
- •Preparing Pins for Permutability
- •Search Order Variable
- •Syntax
- •Macros
- •Setting the permuteRule Property in the Symbol Master
- •Setting the permuteRule Property in the Device Master
- •Setting the permuteRule Property in the Symbol Instance
- •Setting the permuteRule Property in the Device Instance
- •Setting the permuteRule Property in the Component Description Format
- •Preparing Instances for Hierarchical Connectivity Checking
- •Setting Up Your Desktop
- •Customizing Your Desktop Layout
- •Using Multiple Cellviews
- •Printing to the Command Interpreter Window
- •Changing Display Colors
- •Using Bindkeys
- •Displaying Bindkeys
- •Loading Virtuoso XL Bindkeys
- •Setting Environment Variables
- •Information About Online Forms
- •Layout XL Options Form
- •Introduction to Abutment
- •Abutment Requirements
- •Setting Up Cells for Abutment
- •abutAccessDir
- •abutClass
- •Steps in Auto-Abutment
- •Sample Parameterized Cells Set Up for Abutment
- •Example 1
- •Example 2
- •Creating CMOS Pcells to Use with Abutment
- •autoAbutment Properties
- •The abutMosStretchMat Property
- •abutMosStretchMat Rules for MOS Abutment
- •Example Code Setting MOS Abutment Properties
- •Setting Environment Variables for Abutment
- •Move Together
- •Constraint Assisted
- •Using Device Abutment
- •Generating Your Layout with Virtuoso XL Layout Editor
- •Starting Virtuoso XL from the Schematic
- •Importing a Netlist for a Connectivity Reference
- •Starting Virtuoso XL from the Layout View
- •Connectivity Reference as a Netlist
- •Mapping File Structure
- •Working with Template Files
- •Saving Form Contents
- •Loading Template Files
- •Modifying Templates
- •Loading Template Files
- •Creating Template Files
- •Template File Syntax
- •General Syntax Rules
- •Boundaries Section
- •I/O Pins Section
- •Sample Template
- •Generating a Layout with Components Not Placed (Gen From Source)
- •Moving Components from the Schematic into the Layout (Pick from Schematic)
- •Placing a Group of Schematic Elements Together
- •Placing Individual Components
- •Generating Pins
- •Viewing Unplaced Instances/Pins
- •Viewing in Place
- •Manually Abutting Devices Using Pick from Schematic
- •Cloning Components
- •Cloning
- •Troubleshooting
- •Cloning Using Multiple Cellviews
- •Using Correspondence Points
- •Information About Online Forms
- •Add Correspondence Pairs Form
- •Cloning Form
- •Correspondence Pairs Form
- •Import XL Netlist Form
- •Layout Generation Options Form
- •Open File Form
- •Pick from Schematic Form
- •Remove Correspondence Components Form
- •Set Pin Label Text Style Form
- •Startup Option Form
- •Template File Form
- •Editing Your Layout with Virtuoso XL Layout Editor
- •Identifying Incomplete Nets
- •Moving Objects Manually in the Virtuoso XL Layout Editor
- •Moving Objects Using Move Options
- •Setting the Move Form to Appear Automatically
- •Aligning Objects
- •Post Selecting Devices
- •PreSelecting Devices
- •Swapping Components
- •Permuting Component Pins
- •Permuting Pins Manually
- •Checking Permutation Information
- •Using Device Locking
- •Using Automatic Spacing
- •Using Interactive Device Abutment
- •Setting Component Types
- •About Component Types
- •MOS Transistor Stacking and Folding Parameters
- •Modifying a Component Type
- •Using Transistor Chaining
- •Using Transistor Folding
- •Controlling the Folding Grid
- •Folding Transistors
- •Adding Instances to a Layout
- •Adding Pins to a Layout
- •Assigning Pins to a Net
- •Maintaining Connectivity When Editing a Flattened Pcell
- •Information About Online Forms
- •Assign Nets Form
- •Edit Component Types Form
- •Move Form
- •Set Transistor Folding Form
- •Show Incomplete Nets Form
- •Stretch Form
- •Virtuoso XL Alignment Form
- •Using the Virtuoso Custom Placer
- •Overview
- •Main Features
- •Place Menu Command Summary
- •Other Commands Used with the Virtuoso custom placer
- •Placement Styles
- •Setting Up the Virtuoso XL Layout Editor for Placement
- •Identifying the Placement Translation Rules
- •Setting Cadence Design Framework II Environment Variables
- •Setting Environment Variables for the Virtuoso Custom Router and Placer
- •Setting MOS Chaining and Folding Parameters
- •Abutting Standard Cells
- •Using Auto-Abutment During Placement
- •Placement Constraints
- •Constraint Manager Geometric Constraints
- •Pin Placement Constraints
- •Constraint Limitations
- •Placement Parameters and Component Types
- •MOS Transistor Chaining and Folding Parameters
- •Pin Placement
- •Assigning Pins to an Edge
- •Assigning Pins to a Fixed Position
- •Railing Pins
- •Loading the Template File
- •Assigning Spacing Between Pins
- •Saving Pin Placement to a Template File
- •Partitioning the Design
- •Creating a Partition
- •Loading the Template File
- •Saving Partitions to a Template File
- •Setting Placement Planning
- •Assisted CMOS Placement
- •Choose Component Types Form
- •Running the Virtuoso Custom Placer
- •Prerequisites to Placement
- •Running the Virtuoso Custom Placer: Initial Placement
- •Stopping the Placer
- •Running Load Balancing Service (LBS)
- •Troubleshooting Placement Results
- •Running the Virtuoso Custom Placer: Detailed Placement
- •Showing Congestions
- •Information About Forms
- •Auto Placer Form
- •Partitioning Form
- •Choose Component Types Form
- •Pin Placement Form
- •Load Template File Form
- •Placement Planning Form (Assisted CMOS)
- •Placement Planning Form (Assisted Standard Cell)
- •Placement Planning Form (Assisted Mixed CMOS/Standard-Cell)
- •Preparing Your Design for Routing in the Virtuoso XL Layout Editor
- •Understanding Connectivity
- •Pseudo-Parallel Connections
- •Selecting Layers
- •Changing Layers
- •Connecting Nets
- •Creating Paths
- •Connecting Nets with Path Stitching
- •Connecting Nets with Design Shapes
- •Checking Connectivity with Flight Lines
- •Checking Connectivity with Markers
- •Finding Markers
- •Explaining Markers
- •Deleting Single Markers
- •Deleting All Markers
- •Using the Virtuoso Compactor on a Routed Design
- •Overview
- •Main Features
- •Wire Editing Commands
- •Virtuoso Custom Router to Virtuoso XL Command Mapping
- •Prerequisites
- •Rule Information
- •Net Connectivity Information
- •Routing Area Boundary
- •Enabling Wire Editing
- •Toggling Between Virtuoso XL and Wire Editing Enabled
- •Loading ASCII Rules Files
- •The Wire Editing Environment
- •Status Banner
- •Preview Wires and Routing Aids
- •Mouse Button Behavior
- •Using Environment Variables
- •Routing Paths
- •Routing a Single Path
- •Routing Multiple Paths
- •Preventing and Checking Design Rule Violations
- •Interactive Checking
- •Same Net Checking
- •Checking Regions
- •Checking Route and Pin Violations
- •Routing Options and Styles
- •Matching Path Width and Pin Widths
- •Matching Path Width and Pin Widths for Multiple Paths
- •Gathering Bus Wires
- •Spacing for Gathered Bus Wires
- •Overriding Bus Spacing
- •Rotating the Bus Cursor
- •Cycling the Control Wire
- •Allowing Redundant Wiring
- •Allowing Orthogonal Jogs
- •Route To Cursor
- •Allow Floating Nets
- •Connecting Multiple Component Pins
- •Pushing Routes and Components
- •Routing Shielded Nets
- •Routing Tandem Layer Pairs
- •Using Vias
- •Changing Layers and Adding Vias
- •Using Vias Patterns on Multiple Paths
- •Legal Via Sites
- •Rotating Vias
- •Pseudo Vias
- •Editing Routed Connections
- •Stretching Paths and Vias
- •Splitting and Stretching Paths
- •Copying Routes
- •Using Critic Wire
- •Compacting Paths Using Pull
- •Displaying Reports
- •Displaying Routing Status Reports
- •Displaying Network Reports
- •Displaying Component Reports
- •Displaying Net Reports
- •Creating Rules Reports
- •Search Reports
- •Saving Reports
- •Setting Constraints
- •Using the Virtuoso Constraint Manager
- •Using .do Files
- •About the Forms
- •Add Via Form
- •Check Routes Form
- •Create Path Form
- •Find File Form
- •Layout
- •Reports Form
- •Route Options Form
- •Save As Form
- •Search Form
- •Split Form
- •Via Pattern Pop-up
- •Reports
- •Route Status Report Window
- •Network Report Window
- •Instance Report Window
- •Net Report Window
- •Rules Report Window
- •Setting Environment Variables
- •Troubleshooting
- •Finding Design Elements (Probing)
- •Probing Hierarchical Designs
- •Removing Probes
- •Exiting the Probe Command
- •Showing the Options Form
- •Checking Shorts and Opens
- •Comparing Design Elements and Parameters (Checking against the Connectivity Source)
- •Information About Online Forms
- •Probe Options Form
- •Updating Design Data in Virtuoso XL
- •Updating Layout Parameters
- •Updating Schematic Parameters
- •Updating Device Correspondence
- •Creating Device Correspondence
- •Needed Mode
- •Computer Aided Mode
- •Updating the Connectivity Reference
- •Changing the Device (Instance) View
- •Information About Online Forms
- •Change Instance View Form
- •Create Device Correspondence
- •Problems with the Interface
- •Invalid Markers from Previous Software Versions
- •Options Form Does Not Appear
- •Virtuoso XL Performance Is Slow
- •Problems with Editing
- •Components Move Slowly
- •Extra Probes Appear
- •Layout Generation Options Form Does Not Keep Values from the Last Entry
- •Parameters Not Updated
- •Schematic Not Editable
- •Warning to Update Your Design Appears at Startup
- •Problems with Connectivity
- •Connections Not Made
- •Incomplete Nets Command Does Not Recognize Connected Pins and Nets
- •Markers for Nonexistent Overlaps and Shorts Appear
- •Path Ends Not Accepted
- •Placement and Routing Do Not Run
- •Virtuoso XL Does Not Recognize Physical Vias
- •Moving Software Executables To a New Location
- •Environment Variables
- •Virtuoso XL Layout Editor
- •alignApplySeparation
- •alignApplySpacings
- •alignDirection
- •alignLayer
- •alignMethod
- •alignSelectionMode
- •alignSeparation
- •allowRotation
- •autoAbutment
- •autoArrange
- •autoPermutePins
- •autoSpace
- •checkTimeStamps
- •ciwWindow
- •compTypeRefLibs
- •constraintAssistedMode
- •createBoundaryLabel
- •crossSelect
- •extractEnable
- •extractStopLevel
- •globalPlacement
- •ignoredParams
- •ignoreNames
- •incNetCycleHilite
- •incNetHiliteLayer
- •infoWindow
- •initAspectRatio
- •initAspectRatioOption
- •initBoundaryLayer
- •initCreateBoundary
- •initCreateInstances
- •initCreateMTM
- •initCreatePins
- •initDoFolding
- •initDoStacking
- •initEstimateArea
- •initGlobalNetPins
- •initIOLabelType
- •initIOPinLayer
- •initIOPinName
- •initPinHeight
- •initPinMultiplicity
- •initPinWidth
- •initPrBoundaryH
- •initPrBoundaryW
- •initSymbolicPins
- •initUtilization
- •layoutWindow
- •lswWindow
- •lxAllowPseudoParallelNets
- •lxDeltaWidth
- •lxFingeringNames
- •lxGenerationOrientation
- •lxGenerationTopLevelOnly
- •lxInitResetSource
- •lxStackMinimalFolding
- •lxStackPartitionParameters
- •lxWidthTolerance
- •maintainConnections
- •mfactorNames
- •mfactorSplit
- •moveAsGroup
- •openWindow
- •optimizePlacement
- •paramTolerance
- •pathProbe
- •pathPurposeList
- •pathSwitchLayer
- •pathSwitchPurpose
- •preserveTerminalContacts
- •probeCycleHilite
- •probeDevice
- •probeHiliteLayer
- •probeInfoInCIW
- •probeNet
- •probePin
- •rowGroundLayer
- •rowGroundName
- •rowGroundWidth
- •rowPowerLayer
- •rowPowerName
- •rowPowerWidth
- •rowSupplyPosition
- •rowSupplySpacing
- •rowMOSSupplyPattern
- •rowSTDAllowFlip
- •rowSTDSupplyPattern
- •rulesFile
- •runTime
- •saveAs
- •saveAsCellName
- •saveAsLibName
- •saveAsViewName
- •schematicWindow
- •setPPConn
- •sfactorNames
- •sfactorParam
- •showIncNetEnable
- •stopList
- •templateFileName
- •traverseMixedHierarchies
- •updateReplacesMasters
- •updateWithMarkers
- •vcpConductorDepth
- •vcpKeepoutDepth
- •viewList
- •Wire Editor
- •allowFloatingNets
- •allowJogs
- •allowRedundantWiring
- •autoAdjustLength
- •autoShield
- •busOverride
- •busOverrideValue
- •busWireSpacing
- •busWireSpacingType
- •checkCornerCorner
- •checkCrosstalk
- •checkLength
- •checkLimitWay
- •checkMaxProcessWireWidth
- •checkMaxStackViaDepth
- •checkMaxTotalVia
- •checkMinMaskEdgeLength
- •checkMinProcessWireWidth
- •checkMiter
- •checkNetOrder
- •checkOffManGridPin
- •checkOffWireGridPin
- •checkPinSpacing
- •checkPolygonWire
- •checkProtected
- •checkReentrantPath
- •checkRegion
- •checkSameNet
- •checkSegment
- •checkStub
- •checkUseLayers
- •checkUseVias
- •checkWireExtension
- •doFile
- •enableBusRouting
- •enableTandemPair
- •gatherBusWires
- •inaccessiblePin
- •interactiveChecking
- •matchPinWidth
- •matchPinWidthValue
- •matchWireWidth
- •multiplePinsConnection
- •pinLargerMaxProcessWidth
- •pinSmallerMinProcessWidth
- •pushComponent
- •pushRouting
- •routeAsManyAsPossible
- •routeToCursor
- •routeToCursorStyle
- •sameNetChecking
- •showTimingMeter
- •showTimingOctagon
- •snapToPinOrigin
- •useDoFile
- •useRulesFile
- •viaAssistance
- •viaPattern
- •Private Environment Variables
- •Virtuoso XL Command Quick Reference
- •Using Spice and CDL For Netlist Driven Layout Generation
- •Introduction
- •Specifying Spice Designs
- •Cell Creation Rules
- •Character Considerations
- •Spice Statements
- •File Level Statements
- •Statements Allowed at File Level or within a Subckt Cell or a Top Level Cell
- •Statements Allowed within a Subckt Cell or a Top Level Cell
- •Spice Design Example
- •CDL Design Example
- •Parameter Resolution
- •Parameter Levels
- •Resolving Parameters
- •Putting the Rules Together (Examples)
- •Parameter Scaling
- •Complete ibuf Example Results
- •Virtuoso XL .do File Commands
- •Rule Hierarchy
- •circuit
- •Syntax
- •Example
- •Syntax
- •Example
- •limit
- •Syntax
- •Example
- •rule
- •Syntax
- •Example
- •Syntax
Virtuoso XL Layout Editor User Guide
Using Spice and CDL For Netlist Driven Layout Generation
val represents a value which may be numeric, a (variable) parameter name or a literal string enclosed in single quotes (4, -2.2, 3.75U, -3.56e-7, ppp, ‘any lit str’)
File Level Statements
First Line of File
The first line of a Spice or CDL file must be a comment.
Format (Spice or CDL) : *|$ {text} * or $ is the comment character text is an optional text string Ex : * this is a Spice or CDL file
.GLOBAL
The .Global statement is used for specifying global nets.
Format (Spice or CDL) : .GLOBAL name{:P|G} …
name is the net name
P or G are optional and represents Power or Ground
Ex : .GLOBAL vdd:P vss:g GNETA
Note: CDL will allow a * before the . of the .GLOBAL statement.
.INCLUDE
The .Include statement is used for including additional spice files from within a spice file.
The file included is treated similar to as if it were specified directly via command. There is no scoping done. However, all cells in an included file must be defined by .subckt or .model statements. If the specified file name supplied is not fully qualified, the run directory will be used as the base directory for the file.
Format (Spice or CDL) : .INCLUDE ‘filename’
filename is the file to be included
Ex : .INCLUDE ‘/cdsabc/mydir/sfile’
Note: CDL will allow a * before the . of the .INCLUDE statement.
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.INC
The .inc keyword is an alias for the .include keyword. See the .include keyword for details.
.OPTION
The .option statement is used for specifying option parameters.
This statement is reserved for specific Spice options, all but one of which are not used by VXL
Spice processing. These options will be read and stored. The one option processed for Spice handling is the scale. The scale factor acts as a multiplier for values such as length, width, area, etc. See the Parameter Resolution section for more details on the use of scale.
Format (Spice or CDL) : .OPTION param{=val} …
param{=val} is the parameter set to an optional, in the parameter list Ex : .OPTION scale=1.1
Note: CDL will allow a * before the . of the .OPTION statement.
.OPTIONS
The .options keyword is an alias for the .option keyword. See the .option keyword for details.
.MODEL
The .model statement is used for defining various types of model cells.
Format (Spice or CDL) : .MODEL name type {param=val}… name is the model name
type is the model type
param=val is an optional parameter set to a value, in the parameter list
The allowable model types are :
■nmos and pmos for mosfet models, which will be created using the ports D,G,S,B
■njf and pjf for jfet models, which will be created using ports D,G,S
■nmf and pmf for mesfet models, which will be created using ports D,G,S
■npn and pnp for BJT (bipolar) models, which will be created using the ports C,B,E
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■d for diode models, which will be created using the ports PLUS,MINUS
■c for capacitor models, which will be created using the ports PLUS,MINUS
■r for resistor models, which will be created using the ports PLUS,MINUS
Ex: .MODEL TN nmos l = 1U w = 4U
.SUBCKT
The .subckt statement is used for defining subckt cells.
Format (Spice) : .SUBCKT name pin … {param=val}… name is the cell name
pin is a pin in the pin list
param=val is an optional parameter set to a value, in the parameter list Ex : .SUBCKT AND O A B L = 3U AS = 1.5P
Format (CDL) : .SUBCKT name {opin} … / {ipin} … {param=val}… name is the cell name
opin is a pin in the output pin list
/ is the separator between the output pin list and the input pin list ipin is a pin in the input pin list
param=val is an optional parameter set to a value, in the parameter list Ex : .SUBCKT AND O / A B L = 3U AS = 1.5P
Note: For the CDL format, there must be at least one pin in the opin or the ipin list. For Spice, port types are specified using the*PORT statement.
.MACRO
The .macro keyword is an alias for the .subckt keyword. See the .subckt keyword for details.
.ENDS
The .ends statement is used for ending a .subcktcell definition.
Format (Spice or CDL) : .ENDS
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.EOM
The .eom keyword is an alias for the .ends keyword. See the .ends keyword for details.
Statements Allowed at File Level or within a Subckt Cell or a Top Level Cell
.PARAM
The .param statement is used for specifying lists of parameters.
Format (Spice or CDL) : .PARAM param=val …
param=val is a parameter set to a value, in the parameter list
Ex : .PARAM w=5U p = wid str= ‘abc’
Note: CDL will allow a * before the . of the .PARAM statement.
Statements Allowed within a Subckt Cell or a Top Level Cell
* PORT
The * PORT statement is used for specifying pins as input or output pins.
Note: The *PORT statement is restricted to Spice only.
Format (Spice) : * PORT type pin …
type is the pin type and can take the values input, output, bidirect tristate, power, ground, supply, open_drain, or unknown pin is a pin in the pin list
Ex : * PORT input i1 i2
Note: For CDL, port types are specified on the.SUBCKT.
Subckt Reference
Format (Spice) : Xabc term … master {param=val}…
Xabc is the instance name
term is a terminal in the terminal list
master is the cell type (aka : master cell)
param=val is a parameter set to a value, in the parameter list
Ex : xanda a b o AND w=10U qqq=20
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Format (CDL) : Xabc term … {/}master {param=val}…
Xabc is the instance name
term is a terminal in the terminal list
/ is the optional separator between the term list and the cell type master is the cell type (aka : master cell)
param=val is a parameter set to a value, in the parameter list Ex : xanda a b o / AND w=10U qqq=20
Note: Subckt references must always begin with x.
Mosfet Reference
Format (Spice or CDL) : Mabc drain gate src bulk master {val1 {val2}}{param=val}… Mabc is the instance name
drain gate src bulk is the order of the terminals
master is the cell type (ie : model name) (aka : master cell) val1 is the value of the W parameter
val2 is the value of the L parameter
param=val is a parameter set to a value, in the parameter list Ex 1 : m1 vdd a q vdd TP W = 9e-7 L=1U as = 2e-12
Ex 2 : m1 vdd a q vdd TP 9e-7 1U as = 2e-12
Ex 3: m1 vdd a q vdd TP wpa L=lpa
Note: Mosfet references must always begin with m.
Jfet Reference
Format (Spice or CDL) : Jabc drain gate src master {area} {OFF} {param=val}… Jabc is the instance name
drain gate src is the order of the terminals
master is the cell type (ie : model name) (aka : master cell)
area is the optional area factor, it will be assigned to the property
“AREA”
OFF is the optional initial condition flag for dc analysis param=val is a parameter set to a value, in the parameter list
Ex : J1 vdd a q 9e-7 OFF pp = 5
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Note: Jfet references must always begin with j.
Mesfet Reference
Format (Spice or CDL) : Zabc drain gate src master {area} {OFF} {param=val}… Zabc is the instance name
drain gate src is the order of the terminals
master is the cell type (ie : model name) (aka : master cell)
area is the optional area factor, it will be assigned to the property
“AREA”
OFF is the optional initial condition flag for dc analysis param=val is a parameter set to a value, in the parameter list
Ex : Z1 vdd a q 9e-7 OFF pp = 5
Note: Mesfet references must always begin with z.
BJT (Bipolar) Reference
Format (Spice or CDL) :
Qabc collector base emitter substrate master {area} {OFF} {param=val}… Qabc is the instance name
collector base emitter substrate is the order of the terminals master is the cell type (ie : model name) (aka : master cell)
area is the optional area factor, it will be assigned to the property
“AREA”
OFF is the optional initial condition flag for dc analysis param=val is a parameter set to a value, in the parameter list
Ex : Q1 vdd a q 9e-7 OFF pp = 5
Note: BJT references must always begin with q.
Note: The substrate node must be specified. If it is not, a syntax error will occur.
Diode Reference
Format (Spice or CDL) : Dabc term1 term2 master {area} {OFF} {param=val}…
Dabc is the instance name
drain gate src is the order of the terminals
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master is the cell type (ie : model name) (aka : master cell)
area is the optional area factor, it will be assigned to the property
“AREA”
OFF is the optional initial condition flag for dc analysis param=val is a parameter set to a value, in the parameter list
Ex : D1 vdd a 9e-7 OFF pp = 5
Note: Diode references must always begin with d.
Capacitor Reference
Format (Spice or CDL) : Cabc term1 term2 {numval}{model} {param=val}… Cabc is the capacitor name
term1 term2 are the terminals
numval is the optional numerical capacitance value model is the optional model name (aka : master cell)
param=val is a parameter set to a value, in the parameter list Ex 1 : c0 gnd q 1e-14
Ex 2 : c1 gnd q capmod
Note: Either numval or model must be specified. It is allowable to specify both.
Note: Capacitor references must always begin with c.
Resistor Reference
Format (Spice or CDL) : Rabc term1 term2 {numval}{model} {param=val}… Rabc is the resistor name
term1 term2 are the terminals
numval is the optional numerical resistance value model is the optional model name (aka : master cell)
param=val is a parameter set to a value, in the parameter list Ex 1 : r0 gnd q 1e-6
Ex 2 : r1 gnd q resmod
Note: Either numval or model must be specified. It is allowable to specify both.
Note: Resistor references must always begin with r.
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