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Virtuoso XL Layout Editor User Guide

13

Updating Design Data in Virtuoso XL

This chapter explains how to use the Virtuoso® XL layout editor (Virtuoso XL) to make design changes and update your design as you progress. This chapter contains information about the following areas:

Updating Components and Nets (Engineering Change Order Mode) on page 456

Updating Layout Parameters on page 461

Updating Schematic Parameters on page 463

Updating Device Correspondence on page 465

Updating the Connectivity Reference on page 472

Changing the Device (Instance) View on page 473

Information about Virtuoso XL online forms is at the end of the chapter.

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Updating Components and Nets

(Engineering Change Order Mode)

You can automatically update the layout to add any devices, pins, or connectivity changes you have added to the schematic. This operation is sometimes known as Engineering Change

Order (ECO) mode.

It is helpful to have Show Incomplete Nets active when you update components and nets so that you can see that the connectivity you want is made.

To update the components and nets in a layout with changes made to the schematic, follow these steps.

1.Extract the schematic by choosing from the schematic window

Check – Current Cellview.

The schematic editor extracts the connectivity of the design and reports the results in a Schematic Check information window.

2.From the layout window, choose Connectivity – Update – Components and Nets.

Virtuoso XL checks the components and nets in the schematic against the ones in the layout.

If the schematic has changed a Virtuoso XL a dialog box appears indicating that schematic extraction is needed to continue. If you click OK in the dialog box, then Virtuoso XL extracts the schematic hierarchically including the reference libraries. However, the extracted cellviews are not automatically saved.

If you want a different extraction behavious click Cancel in the dialog box and invoke the CheckHierarchy command in the schematic window.

If there are no differences, a message appears in the Command Interpreter Window

(CIW) saying that the check has been completed successfully. If there are differences, the differences are displayed in the CIW.

If devices are found in the layout that are not in the schematic, they are displayed with markers.

If devices or pins in the schematic are missing from the layout, the Layout Generation

Options form opens. For more information about using this form, see the Layout Generation Options Form on page 196.

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If the I/O Pins option is turned on, the pins shown in the I/O Pins section of the form are those that exist in the schematic but are missing from the layout.

Note: the Layout Generation Options form always reflects the default settings for the design; that is, the state of the schematic, not the entries from the previous time the form was used.

3. In the Layout Generation section at the top of the form,

a. If you want to generate pins, instances, or a boundary as specified in the schematic or in a template file, check that the options you want are turned on.

Note: Update Components and Nets only chains or folds new devices after running the Layout Generation Options with chaining and folding. New chains are separate and do not attach to old chains. Devices that had been chained previously to running Update Components and Nets are not moved from their existing positions.

Recreate the abutment into stacks of MOS transistors or fingers of folded MOS transistors that were unabutted since you created them with the Design-Gen From

Source command

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Recreate and fold MOS transistors that were unfolded or all fingers of which were deleted since you created them with the Design – Gen From Source command

If the Transistor Chaining and Transistor Folding options are off, and you have deleted all the fingers of a folded transistor,Update Components and Nets generates a single device. If you have deleted some of the fingers of a folded device, it creates markers only if fingers in a numbered sequence are missing; otherwise it does nothing about missing fingers of folded transistors.

Note:

b.If you want to preserve existing many-to-many mapping of devices between the connectivity source and the layout, turn on Preserve Mappings.

Note: The Preserve Mappings functionality does not report missing devices or shapes within a mapped group.

4.For each pin you want to add, click Add a Pin.

An empty pin row opens.

5.For each pin you want to add in the new pin row

a.In the Net Name column, type in a net name.

b.In the Pin Type cyclic field, choose a pin type.

c.In the Layer/Master cyclic field, choose a layer.

d.In the Width field, specify the pin width.

e.In the Height field, specify the pin height.

f.In the Num field, specify the number of pins you want.

6.For all pins set the Pin Label Shape.

a.Set Label to generate labels for each pin on the text dg layer purpose pair.

b.Set Text Display to generate text for each pin on the text dg layer purpose pair.

To view the text, set the Pin Names option on in the Display Options form.

c.Set None to not generate labels for pins.

7.To set the style of the pin labels, click Display Pin Name Option....

The Display Pin Name Option form appears.

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8.Choose the options you want from the Set Pin Label Text Style form and click OK.

9.In the Boundary section of the Layout Generation Options form, if you want Virtuoso XL to draw a boundary, follow these steps.

a.In the Layer field, choose the layer you want to use for the boundary.

b.In the Shape field, chooseRectangle or Polygon.

To specify the dimensions of a rectangular boundary, you can use only two of the following four values: Utilization %, Aspect Ratio (Width/Height), Boundary Width, or Boundary Height. You can also type in the Points field values for the Left (X coordinate) side of the boundary and the Bottom (Y coordinate) side of the boundary in this format: (0 0) (10 10).

To specify the dimensions of a polygonal boundary, choose Polygon from the Shape field and enter the X and Y coordinates of each angle of the polygon in the Points type-in field in the following format. For example, for a rectangle:0( 0) (0 10)

(10 8) (8 0) (0 0)

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When you move the cursor in the layout window, the X and Y coordinates of the location of the cursor are displayed in the Status Line at the top of the layout window.

10.In the Template File section, to load a template file, (an ASCII file containing the information entered in this form in a previous session and saved to a file) follow these steps.

a.Select the Load Template File for Layout Generation option.

b.Click the Browse button and the Open File form appears.

c.Click on the directories in the left list box to descend into your file hierarchy until you reach the name of the template file to use.

d.Click on the name of the template file in the right list box to enter it in theName field.

The left and right arrows at the right side of the form let you go up and down in the file hierarchy.

e.Click OK in the Open File form.

The values in the template file are loaded into the Layout Generation Options form and are used during the design session.

You can set an environment variable, templateFileName, to always load the name of a template you specify as the value of the variable.

11.To save the information you enter in the Layout Generation Options form from the cellview to a template file (an ASCII file) to use in a later session., follow these steps.

a.Select Design-Save To Template. The Template File form appears.

b.Turn on the Boundary an I/O Pins options

c.In the Template file name filed type in a template file name

<design_name.lxt>.

d.Click OK.

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