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Virtuoso XL Layout Editor User Guide

Preparing Your Connectivity Source for the Virtuoso XL Layout Editor

The figure below shows the views the software chooses if you use the empty string (“ ”) value on a view. The chosen layout views are shown with thick-line boxes.

chosen layout view

Top Cell

schematic

layout Mux

schematic symbol

NMOS NMOS PMOS PMOS

 

 

 

symbol

symbol

symbol

symbol

layout

layout

layout

layout

AND

cmos.sch symbol layoutS

property=lxStopList value=" "

NMOS NMOS PMOS PMOS

symbol symbol symbol symbol

layoutS

layoutS

layoutS

layoutS

This time, the software first stops at the AND cell that has a view listed in the stop list, but the view has the lxStopList property set to the empty string (“ ”), so the software does not stop there and descends into the views in the level below and stops at the next views that are listed in the stop list.

For a more detailed explanation of hierarchy expansion using the lxStopList and lxViewList properties, see “How the Netlister Expands Hierarchy” inChapter 3 of the

Cadence Analog Circuit Design Environment User Guide.

Using the lxCombination Property to Build Complex Devices

lxCombination is a user defined property used to build a complex set of devices, which is comprised of series (sfactor) and parallel (mfactor) connections. To generate these complex devices, lxCombination needs to be defined as a CDF parameter or an instance property, using a valid string type value.

For example, you can use lxCombination to divide a single resistor in the schematic into a complex set of devices in the layout:

(2k*2)/3+1500/4

where

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Preparing Your Connectivity Source for the Virtuoso XL Layout Editor

2k, 2, 3, 1500, and 4 are device parameter values (positive integers)

* and + are series connections

/ is a parallel connection

Note: The difference between the series connections is + can be followed by an expression, whereas * can only be followed by an integer (the / parallel connection can also only be followed by an integer).

In the schematic cellview, a resistor with the name A and a resistance of 3k is connected to nets net1 and net2.

Schematic

Layout

 

 

 

 

 

net1

 

 

 

net1

2k

2k

2k

 

 

( 2k * 2 ) / 3 + 1500/ 4

 

 

 

 

R=3k

A

2k

2k

2k

 

 

net2

1.5k

1.5k

1.5k

1.5k

 

 

 

net2

 

 

The lxCombination property is defined on this instance with a value of3k. Virtuoso XL layout generation reads the lxCombination property and ignores the 3k value. A total of 10 resistors are generated in a combination of series and parallel connections, based on the property value. In this example, there are two 2k resistors connected in a series, with each series connected in parallel three times. Also connected in series to the 2k resistors are four parallel connected 1.5k resistors.

The advantages of generating a set of complex layout devices from a single schematic device are as follows:

Achieves maximum density by putting the resistors into spaces otherwise not utilized

Facilitates creating a close approximate of the resistance value as defined in the schematic, without violating the manufacturing grid

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Preparing Your Connectivity Source for the Virtuoso XL Layout Editor

Using the lxNetNamePrefix Property to Add Prefixes to Nets

The names of the internal nets are generated in the layout using Virtuoso XL layout editor conventions.You can use the lxNetNamePrefix property to add unique prefixes to the internal nets (valid values: string).

Note: lxNetNamePrefix can only be used with devices which have the lxCombination property or sfactor parameter.

For example, generating layout devices from the R device in the schematic adds |R|netMS1, |R|netMS2, and |R|netMS3 names to the internal nets.

Schematic

Layout

 

 

 

 

 

net1

 

 

 

net1

2k

2k

2k

 

 

 

 

 

 

 

 

|R|netMS1

|R|netMS2

|R|netMS3

R=3k

A

2k

2k

2k

 

 

net2

1.5k

1.5k

1.5k

1.5k

 

 

 

 

 

net2

Using the lxNetNamePrefix property, you can choose to add the prefixX to the internal net names. The names change to |R|XnetMS1, |R|XnetMS2, and |R|XnetMS3.

Layout

 

net1

 

 

2k

2k

2k

 

 

 

 

|R|XnetMS1 |R|XnetMS2 |R|XnetMS3

2k

2k

2k

 

1.5k

1.5k

1.5k

1.5k

 

 

 

net2

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