- •Features
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •Resources
- •Data Retention
- •Capacitive touch sensing
- •AVR CPU Core
- •Introduction
- •Status Register
- •Stack Pointer
- •I/O Memory
- •Overview
- •Timing
- •Using all Locations of External Memory Smaller than 64 Kbyte
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Register Description for I/O Ports
- •8-bit Timer/Counter0 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Noise Canceler
- •Force Output Compare
- •Normal Mode
- •Fast PWM Mode
- •16-bit Timer/Counter Register Description
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter2 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Output Compare Modulator (OCM1C2)
- •Overview
- •Description
- •Timing Example
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Dual USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Frame Formats
- •Parity Bit Calculation
- •Parity Generator
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Using MPCM
- •Features
- •TWI Terminology
- •Transferring Bits
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •Scl and SDA Pins
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •Using the TWI
- •Master Receiver Mode
- •Slave Receiver Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •Analog Input Circuitry
- •Features
- •Overview
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Reset Register
- •EXTEST; $0
- •IDCODE; $1
- •AVR_RESET; $C
- •BYPASS; $F
- •Scanning the ADC
- •ATmega128 Boundary-scan Order
- •Application Section
- •Programming Time for Flash when Using SPM
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Programming Command Register
- •Virtual Flash Page Read Register
- •Performing Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •Speed Grades
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics
- •External Data Memory Timing
- •Idle Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega128 Rev. F to M
ATmega128
Ordering Information
Speed (MHz) |
Power Supply |
Ordering Code(1) |
Package(2) |
Operation Range |
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ATmega128L-8AU |
64A |
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8 |
2.7 – 5.5V |
ATmega128L-8AUR(3) |
64A |
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ATmega128L-8MU |
64M1 |
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ATmega128L-8MUR(3) |
64M1 |
Industrial |
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ATmega128-16AU |
64A |
(-40oC to 85oC) |
16 |
4.5 – 5.5V |
ATmega128-16AUR(3) |
64A |
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ATmega128-16MU |
64M1 |
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ATmega128-16MUR(3) |
64M1 |
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ATmega128L–8AN |
64A |
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8 |
3.0 – 5.5V |
ATmega128L–8ANR(3) |
64A |
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ATmega128L–8MN |
64M1 |
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ATmega128L–8MNR(3) |
64M1 |
Extended |
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ATmega128–16AN |
64A |
(-40°C to 105°C) |
16 |
4.5 – 5.5V |
ATmega128–16ANR(3) |
64A |
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ATmega128–16MN |
64M1 |
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ATmega128–16MNR(3) |
64M1 |
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Notes: 1. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
2.The device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
3.Tape and Reel
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Package Type |
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64A |
64-lead, 14 x 14 x 1.0mm, Thin Profile Plastic Quad Flat Package (TQFP) |
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64M1 |
64-pad, 9 x 9 x 1.0mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) |
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368
2467X–AVR–06/11
ATmega128
Packaging Information
64A
PIN 1 |
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B |
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e |
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PIN 1 IDENTIFIER |
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E1 E
D1
D
C 
0°~7°
A1
A2 A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2.Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL |
MIN |
NOM |
MAX |
NOTE |
A |
– |
– |
1.20 |
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A1 |
0.05 |
– |
0.15 |
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A2 |
0.95 |
1.00 |
1.05 |
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D |
15.75 |
16.00 |
16.25 |
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D1 |
13.90 |
14.00 |
14.10 |
Note 2 |
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E |
15.75 |
16.00 |
16.25 |
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E1 |
13.90 |
14.00 |
14.10 |
Note 2 |
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B |
0.30 |
– |
0.45 |
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C |
0.09 |
– |
0.20 |
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L |
0.45 |
– |
0.75 |
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e |
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0.80 TYP |
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2010-10-20
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2325 Orchard Parkway |
TITLE |
DRAWING NO. |
REV. |
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64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, |
64A |
C |
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R San Jose, CA 95131 |
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) |
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369
2467X–AVR–06/11
ATmega128
64M1
D 
Marked Pin# 1 ID
E
TOP VIEW |
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K |
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L |
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Pin #1 Corner |
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D2 |
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1 |
Option A |
Pin #1 |
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2 |
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Triangle |
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3 |
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E2 |
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Option B |
Pin #1 |
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Chamfer |
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(C 0.30) |
K |
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Option C |
Pin #1 |
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b |
e |
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Notch |
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(0.20 R) |
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BOTTOM VIEW
Notes:
C SEATING PLANE
A1
A 
0.08 C
SIDE VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL |
MIN |
NOM |
MAX |
NOTE |
A |
0.80 |
0.90 |
1.00 |
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A1 |
– |
0.02 |
0.05 |
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b |
0.18 |
0.25 |
0.30 |
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D |
8.90 |
9.00 |
9.10 |
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D2 |
5.20 |
5.40 |
5.60 |
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E |
8.90 |
9.00 |
9.10 |
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E2 |
5.20 |
5.40 |
5.60 |
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e |
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0.50 BSC |
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L |
0.35 |
0.40 |
0.45 |
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K |
1.25 |
1.40 |
1.55 |
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1.JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
2.Dimension and tolerance conform to ASMEY14.5M-1994.
2010-10-19
|
2325 Orchard Parkway |
TITLE |
|
64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, |
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San Jose, CA 95131 |
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R |
5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) |
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DRAWING NO. REV.
64M1 H
370
2467X–AVR–06/11