- •Features
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •Resources
- •Data Retention
- •Capacitive touch sensing
- •AVR CPU Core
- •Introduction
- •Status Register
- •Stack Pointer
- •I/O Memory
- •Overview
- •Timing
- •Using all Locations of External Memory Smaller than 64 Kbyte
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Register Description for I/O Ports
- •8-bit Timer/Counter0 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Noise Canceler
- •Force Output Compare
- •Normal Mode
- •Fast PWM Mode
- •16-bit Timer/Counter Register Description
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter2 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Output Compare Modulator (OCM1C2)
- •Overview
- •Description
- •Timing Example
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Dual USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Frame Formats
- •Parity Bit Calculation
- •Parity Generator
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Using MPCM
- •Features
- •TWI Terminology
- •Transferring Bits
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •Scl and SDA Pins
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •Using the TWI
- •Master Receiver Mode
- •Slave Receiver Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •Analog Input Circuitry
- •Features
- •Overview
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Reset Register
- •EXTEST; $0
- •IDCODE; $1
- •AVR_RESET; $C
- •BYPASS; $F
- •Scanning the ADC
- •ATmega128 Boundary-scan Order
- •Application Section
- •Programming Time for Flash when Using SPM
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Programming Command Register
- •Virtual Flash Page Read Register
- •Performing Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •Speed Grades
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics
- •External Data Memory Timing
- •Idle Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega128 Rev. F to M
ATmega128
ATmega128
Boundary-scan
Order
Table 106 shows the Scan order between TDI and TDO when the Boundary-scan Chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the analog circuits, which constitute the most significant bits of the scan chain regardless of which physical pin they are connected to. In Figure 124, PXn. Data corresponds to FF0, PXn. Control corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.
Table 106. ATmega128 Boundary-scan Order
Bit Number |
Signal Name |
Module |
|
|
|
204 |
AC_IDLE |
Comparator |
|
|
|
203 |
ACO |
|
|
|
|
202 |
ACME |
|
|
|
|
201 |
AINBG |
|
|
|
|
200 |
COMP |
ADC |
|
|
|
199 |
PRIVATE_SIGNAL1(1) |
|
198 |
ACLK |
|
|
|
|
197 |
ACTEN |
|
|
|
|
196 |
PRIVATE_SIGNAL1(2) |
|
195 |
ADCBGEN |
|
|
|
|
194 |
ADCEN |
|
|
|
|
193 |
AMPEN |
|
|
|
|
192 |
DAC_9 |
|
|
|
|
191 |
DAC_8 |
|
|
|
|
190 |
DAC_7 |
|
|
|
|
189 |
DAC_6 |
|
|
|
|
188 |
DAC_5 |
|
|
|
|
187 |
DAC_4 |
|
|
|
|
186 |
DAC_3 |
|
|
|
|
185 |
DAC_2 |
|
|
|
|
184 |
DAC_1 |
|
|
|
|
183 |
DAC_0 |
|
|
|
|
182 |
EXTCH |
|
|
|
|
181 |
G10 |
|
|
|
|
180 |
G20 |
|
|
|
|
179 |
GNDEN |
|
|
|
|
178 |
HOLD |
|
|
|
|
177 |
IREFEN |
|
|
|
|
176 |
MUXEN_7 |
|
|
|
|
266
2467X–AVR–06/11
ATmega128
Table 106. ATmega128 Boundary-scan Order (Continued)
Bit Number |
Signal Name |
Module |
|
|
|
175 |
MUXEN_6 |
ADC |
|
|
|
174 |
MUXEN_5 |
|
|
|
|
173 |
MUXEN_4 |
|
|
|
|
172 |
MUXEN_3 |
|
|
|
|
171 |
MUXEN_2 |
|
|
|
|
170 |
MUXEN_1 |
|
|
|
|
169 |
MUXEN_0 |
|
|
|
|
168 |
NEGSEL_2 |
|
|
|
|
167 |
NEGSEL_1 |
|
|
|
|
166 |
NEGSEL_0 |
|
|
|
|
165 |
PASSEN |
|
|
|
|
164 |
PRECH |
|
|
|
|
163 |
SCTEST |
|
|
|
|
162 |
ST |
|
|
|
|
161 |
VCCREN |
|
|
|
|
160 |
PEN |
Programming enable (observe only) |
|
|
|
159 |
PE0.Data |
Port E |
|
|
|
158 |
PE0.Control |
|
|
|
|
157 |
PE0.Pullup_Enable |
|
|
|
|
156 |
PE1.Data |
|
|
|
|
155 |
PE1.Control |
|
|
|
|
154 |
PE1.Pullup_Enable |
|
|
|
|
153 |
PE2.Data |
|
|
|
|
152 |
PE2.Control |
|
|
|
|
151 |
PE2.Pullup_Enable |
|
|
|
|
150 |
PE3.Data |
|
|
|
|
149 |
PE3.Control |
|
|
|
|
148 |
PE3.Pullup_Enable |
|
|
|
|
147 |
PE4.Data |
|
|
|
|
146 |
PE4.Control |
|
|
|
|
145 |
PE4.Pullup_Enable |
|
|
|
|
144 |
PE5.Data |
|
|
|
|
143 |
PE5.Control |
|
|
|
|
142 |
PE5.Pullup_Enable |
|
|
|
|
141 |
PE6.Data |
|
|
|
|
140 |
PE6.Control |
|
|
|
|
267
2467X–AVR–06/11
ATmega128
Table 106. ATmega128 Boundary-scan Order (Continued)
Bit Number |
Signal Name |
Module |
|
|
|
139 |
PE6.Pullup_Enable |
Port E |
|
|
|
138 |
PE7.Data |
|
|
|
|
137 |
PE7.Control |
|
|
|
|
136 |
PE7.Pullup_Enable |
|
|
|
|
135 |
PB0.Data |
Port B |
|
|
|
134 |
PB0.Control |
|
|
|
|
133 |
PB0.Pullup_Enable |
|
|
|
|
132 |
PB1.Data |
|
|
|
|
131 |
PB1.Control |
|
|
|
|
130 |
PB1.Pullup_Enable |
|
|
|
|
129 |
PB2.Data |
|
|
|
|
128 |
PB2.Control |
|
|
|
|
127 |
PB2.Pullup_Enable |
|
|
|
|
126 |
PB3.Data |
|
|
|
|
125 |
PB3.Control |
|
|
|
|
124 |
PB3.Pullup_Enable |
|
|
|
|
123 |
PB4.Data |
|
|
|
|
122 |
PB4.Control |
|
|
|
|
121 |
PB4.Pullup_Enable |
|
|
|
|
120 |
PB5.Data |
|
|
|
|
119 |
PB5.Control |
|
|
|
|
118 |
PB5.Pullup_Enable |
|
|
|
|
117 |
PB6.Data |
|
|
|
|
116 |
PB6.Control |
|
|
|
|
115 |
PB6.Pullup_Enable |
|
|
|
|
114 |
PB7.Data |
|
|
|
|
113 |
PB7.Control |
|
|
|
|
112 |
PB7.Pullup_Enable |
|
|
|
|
111 |
PG3.Data |
Port G |
|
|
|
110 |
PG3.Control |
|
|
|
|
109 |
PG3.Pullup_Enable |
|
|
|
|
108 |
PG4.Data |
|
|
|
|
107 |
PG4.Control |
|
|
|
|
106 |
PG4.Pullup_Enable |
|
|
|
|
105 |
TOSC |
32kHz Timer Oscillator |
|
|
|
104 |
TOSCON |
|
|
|
|
268
2467X–AVR–06/11
ATmega128
Table 106. ATmega128 Boundary-scan Order (Continued)
Bit Number |
Signal Name |
Module |
|
|
|
|
|
103 |
RSTT |
Reset Logic |
|
|
|
(Observe-only) |
|
102 |
RSTHV |
||
|
|||
|
|
|
|
101 |
EXTCLKEN |
Enable signals for main Clock/Oscillators |
|
|
|
|
|
100 |
OSCON |
|
|
|
|
|
|
99 |
RCOSCEN |
|
|
|
|
|
|
98 |
OSC32EN |
|
|
|
|
|
|
97 |
EXTCLK (XTAL1) |
Clock input and Oscillators for the main clock |
|
|
|
(Observe-only) |
|
96 |
OSCCK |
||
|
|||
|
|
|
|
95 |
RCCK |
|
|
|
|
|
|
94 |
OSC32CK |
|
|
|
|
|
|
93 |
TWIEN |
TWI |
|
|
|
|
|
92 |
PD0.Data |
Port D |
|
|
|
|
|
91 |
PD0.Control |
|
|
|
|
|
|
90 |
PD0.Pullup_Enable |
|
|
|
|
|
|
89 |
PD1.Data |
|
|
|
|
|
|
88 |
PD1.Control |
|
|
|
|
|
|
87 |
PD1.Pullup_Enable |
|
|
|
|
|
|
86 |
PD2.Data |
|
|
|
|
|
|
85 |
PD2.Control |
|
|
|
|
|
|
84 |
PD2.Pullup_Enable |
|
|
|
|
|
|
83 |
PD3.Data |
|
|
|
|
|
|
82 |
PD3.Control |
|
|
|
|
|
|
81 |
PD3.Pullup_Enable |
|
|
|
|
|
|
80 |
PD4.Data |
|
|
|
|
|
|
79 |
PD4.Control |
|
|
|
|
|
|
78 |
PD4.Pullup_Enable |
|
|
|
|
|
|
77 |
PD5.Data |
|
|
|
|
|
|
76 |
PD5.Control |
|
|
|
|
|
|
75 |
PD5.Pullup_Enable |
|
|
|
|
|
|
74 |
PD6.Data |
|
|
|
|
|
|
73 |
PD6.Control |
|
|
|
|
|
|
72 |
PD6.Pullup_Enable |
|
|
|
|
|
|
71 |
PD7.Data |
|
|
|
|
|
|
70 |
PD7.Control |
|
|
|
|
|
|
69 |
PD7.Pullup_Enable |
|
|
|
|
|
|
68 |
PG0.Data |
Port G |
|
|
|
|
269
2467X–AVR–06/11
ATmega128
Table 106. ATmega128 Boundary-scan Order (Continued)
Bit Number |
Signal Name |
Module |
|
|
|
67 |
PG0.Control |
Port G |
|
|
|
66 |
PG0.Pullup_Enable |
|
|
|
|
65 |
PG1.Data |
|
|
|
|
64 |
PG1.Control |
|
|
|
|
63 |
PG1.Pullup_Enable |
|
|
|
|
62 |
PC0.Data |
Port C |
|
|
|
61 |
PC0.Control |
|
|
|
|
60 |
PC0.Pullup_Enable |
|
|
|
|
59 |
PC1.Data |
|
|
|
|
58 |
PC1.Control |
|
|
|
|
57 |
PC1.Pullup_Enable |
|
|
|
|
56 |
PC2.Data |
|
|
|
|
55 |
PC2.Control |
|
|
|
|
54 |
PC2.Pullup_Enable |
|
|
|
|
53 |
PC3.Data |
|
|
|
|
52 |
PC3.Control |
|
|
|
|
51 |
PC3.Pullup_Enable |
|
|
|
|
50 |
PC4.Data |
|
|
|
|
49 |
PC4.Control |
|
|
|
|
48 |
PC4.Pullup_Enable |
|
|
|
|
47 |
PC5.Data |
|
|
|
|
46 |
PC5.Control |
|
|
|
|
45 |
PC5.Pullup_Enable |
|
|
|
|
44 |
PC6.Data |
|
|
|
|
43 |
PC6.Control |
|
|
|
|
42 |
PC6.Pullup_Enable |
|
|
|
|
41 |
PC7.Data |
|
|
|
|
40 |
PC7.Control |
|
|
|
|
39 |
PC7.Pullup_Enable |
|
|
|
|
38 |
PG2.Data |
Port G |
|
|
|
37 |
PG2.Control |
|
|
|
|
36 |
PG2.Pullup_Enable |
|
|
|
|
35 |
PA7.Data |
Port A |
|
|
|
34 |
PA7.Control |
|
|
|
|
33 |
PA7.Pullup_Enable |
|
|
|
|
32 |
PA6.Data |
|
|
|
|
270
2467X–AVR–06/11
ATmega128
Table 106. |
ATmega128 Boundary-scan Order (Continued) |
||
Bit Number |
Signal Name |
Module |
|
|
|
|
|
31 |
|
PA6.Control |
Port A |
|
|
|
|
30 |
|
PA6.Pullup_Enable |
|
|
|
|
|
29 |
|
PA5.Data |
|
|
|
|
|
28 |
|
PA5.Control |
|
|
|
|
|
27 |
|
PA5.Pullup_Enable |
|
|
|
|
|
26 |
|
PA4.Data |
|
|
|
|
|
25 |
|
PA4.Control |
|
|
|
|
|
24 |
|
PA4.Pullup_Enable |
|
|
|
|
|
23 |
|
PA3.Data |
|
|
|
|
|
22 |
|
PA3.Control |
|
|
|
|
|
21 |
|
PA3.Pullup_Enable |
|
|
|
|
|
20 |
|
PA2.Data |
|
|
|
|
|
19 |
|
PA2.Control |
|
|
|
|
|
18 |
|
PA2.Pullup_Enable |
|
|
|
|
|
17 |
|
PA1.Data |
|
|
|
|
|
16 |
|
PA1.Control |
|
|
|
|
|
15 |
|
PA1.Pullup_Enable |
|
|
|
|
|
14 |
|
PA0.Data |
|
|
|
|
|
13 |
|
PA0.Control |
|
|
|
|
|
12 |
|
PA0.Pullup_Enable |
|
|
|
|
|
11 |
|
PF3.Data |
Port F |
|
|
|
|
10 |
|
PF3.Control |
|
|
|
|
|
9 |
|
PF3.Pullup_Enable |
|
|
|
|
|
8 |
|
PF2.Data |
|
|
|
|
|
7 |
|
PF2.Control |
|
|
|
|
|
6 |
|
PF2.Pullup_Enable |
|
|
|
|
|
5 |
|
PF1.Data |
|
|
|
|
|
4 |
|
PF1.Control |
|
|
|
|
|
3 |
|
PF1.Pullup_Enable |
|
|
|
|
|
2 |
|
PF0.Data |
|
|
|
|
|
1 |
|
PF0.Control |
|
|
|
|
|
0 |
|
PF0.Pullup_Enable |
|
|
|
|
|
Notes: 1. |
PRIVATE_SIGNAL1 should always scanned in as zero. |
||
2. PRIVATE_SIGNAL2 should always scanned in as zero.
271
2467X–AVR–06/11
ATmega128
Boundary-scan
Description
Language Files
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format used by automated test-generation software. The order and function of bits in the Boundary-scan Data Register are included in this description.
272
2467X–AVR–06/11