- •Features
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •Resources
- •Data Retention
- •Capacitive touch sensing
- •AVR CPU Core
- •Introduction
- •Status Register
- •Stack Pointer
- •I/O Memory
- •Overview
- •Timing
- •Using all Locations of External Memory Smaller than 64 Kbyte
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Register Description for I/O Ports
- •8-bit Timer/Counter0 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Noise Canceler
- •Force Output Compare
- •Normal Mode
- •Fast PWM Mode
- •16-bit Timer/Counter Register Description
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter2 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Output Compare Modulator (OCM1C2)
- •Overview
- •Description
- •Timing Example
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Dual USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Frame Formats
- •Parity Bit Calculation
- •Parity Generator
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Using MPCM
- •Features
- •TWI Terminology
- •Transferring Bits
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •Scl and SDA Pins
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •Using the TWI
- •Master Receiver Mode
- •Slave Receiver Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •Analog Input Circuitry
- •Features
- •Overview
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Reset Register
- •EXTEST; $0
- •IDCODE; $1
- •AVR_RESET; $C
- •BYPASS; $F
- •Scanning the ADC
- •ATmega128 Boundary-scan Order
- •Application Section
- •Programming Time for Flash when Using SPM
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Programming Command Register
- •Virtual Flash Page Read Register
- •Performing Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •Speed Grades
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics
- •External Data Memory Timing
- •Idle Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega128 Rev. F to M
ATmega128
Master Receiver Mode In the Master Receiver Mode, a number of data bytes are received from a slave transmitter (see Figure 98). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero.
Figure 98. Data Transfer in Master Receiver Mode
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Device 1 |
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Device 2 |
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Device 3 |
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Device n |
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R2 |
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MASTER |
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SLAVE |
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RECEIVER |
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TRANSMITTER |
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SDA
SCL
A START condition is sent by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
1 |
0 |
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TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT flag. The TWI will then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT flag is set by hardware, and the status code in TWSR will be $08 (See Table 88). In order to enter MR mode, SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
0 |
0 |
X |
1 |
0 |
X |
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When SLA+R have been transmitted and an acknowledgment bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are $38, $40, or $48. The appropriate action to be taken for each of these status codes is detailed in Table 97. Received data can be read from the TWDR Register when the TWINT flag is set high by hardware. This scheme is repeated until the last byte has been received. After the last byte has been received, the MR should inform the ST by sending a NACK after the last received data byte. The transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
0 |
1 |
X |
1 |
0 |
X |
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A REPEATED START condition is generated by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
1 |
0 |
X |
1 |
0 |
X |
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After a repeated START condition (state $10) the Two-wire Serial Interface can access the same slave again, or a new slave without transmitting a STOP condition. Repeated START
216
2467X–AVR–06/11
ATmega128
enables the master to switch between slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus.
Figure 99. Formats and States in the Master Receiver Mode
MR
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DATA |
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DATA |
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reception |
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from a slave |
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receiver |
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$08 |
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$50 |
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$58 |
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Next transfer |
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RS |
SLA |
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repeated start |
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slave address |
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$48 |
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address or data byte |
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continues |
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continues |
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$38 |
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continues |
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$68 |
$78 |
$B0 |
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states in slave mode |
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Any number of data bytes |
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and their associated acknowledge bits |
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to a defined state of the Two-wire Serial Bus. The |
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prescaler bits are zero or masked to zero
217
2467X–AVR–06/11
ATmega128
Table 89. Status Codes for Master Receiver Mode
Status Code |
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Application Software Response |
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(TWSR) |
Status of the Two-wire Serial |
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To TWCR |
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Prescaler Bits |
Bus and Two-wire Serial Inter- |
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To/from TWDR |
STA |
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STO |
TWINT |
TWEA |
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are 0 |
face Hardware |
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Next Action Taken by TWI Hardware |
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$08 |
A START condition has been |
Load SLA+R |
0 |
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0 |
1 |
X |
SLA+R will be transmitted |
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transmitted |
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ACK or NOT ACK will be received |
$10 |
A repeated START condition |
Load SLA+R or |
0 |
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0 |
1 |
X |
SLA+R will be transmitted |
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has been transmitted |
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ACK or NOT ACK will be received |
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Load SLA+W |
0 |
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0 |
1 |
X |
SLA+W will be transmitted |
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Logic will switch to master transmitter mode |
$38 |
Arbitration lost in SLA+R or NOT |
No TWDR action or |
0 |
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0 |
1 |
X |
Two-wire Serial Bus will be released and not addressed |
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ACK bit |
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slave mode will be entered |
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No TWDR action |
1 |
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0 |
1 |
X |
A START condition will be transmitted when the bus |
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becomes free |
$40 |
SLA+R has been transmitted; |
No TWDR action or |
0 |
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0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
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ACK has been received |
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returned |
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No TWDR action |
0 |
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0 |
1 |
1 |
Data byte will be received and ACK will be returned |
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$48 |
SLA+R has been transmitted; |
No TWDR action or |
1 |
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0 |
1 |
X |
Repeated START will be transmitted |
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NOT ACK has been received |
No TWDR action or |
0 |
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1 |
1 |
X |
STOP condition will be transmitted and TWSTO flag will |
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be reset |
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No TWDR action |
1 |
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1 |
1 |
X |
STOP condition followed by a START condition will be |
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transmitted and TWSTO flag will be reset |
$50 |
Data byte has been received; |
Read data byte or |
0 |
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0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
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ACK has been returned |
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returned |
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Read data byte |
0 |
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0 |
1 |
1 |
Data byte will be received and ACK will be returned |
$58 |
Data byte has been received; |
Read data byte or |
1 |
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0 |
1 |
X |
Repeated START will be transmitted |
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NOT ACK has been returned |
Read data byte or |
0 |
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1 |
1 |
X |
STOP condition will be transmitted and TWSTO flag will |
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be reset |
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Read data byte |
1 |
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1 |
1 |
X |
STOP condition followed by a START condition will be |
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transmitted and TWSTO flag will be reset |
Slave Receiver Mode In the Slave Receiver mode, a number of data bytes are received from a master transmitter (see Figure 100). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero.
Figure 100. Data Transfer in Slave Receiver Mode
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VCC |
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Device 1 |
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Device 2 |
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Device 3 |
........ |
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Device n |
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R1 |
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R2 |
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SLAVE |
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MASTER |
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RECEIVER |
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TRANSMITTER |
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SDA
SCL
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
TWAR |
TWA6 |
TWA5 |
TWA4 |
TWA3 |
TWA2 |
TWA1 |
TWA0 |
TWGCE |
value |
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Device’s Own Slave Address |
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218
2467X–AVR–06/11
ATmega128
The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore the general call address.
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
X |
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TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgment of the device’s own slave address or the general call address. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been received, the TWINT flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in Table 90. The slave receiver mode may also be entered if arbitration is lost while the TWI is in the master mode (see states $68 and $78).
If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA after the next received data byte. This can be used to indicate that the slave is not able to receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave address. However, the Two-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock low during the wake up and until the TWINT flag is cleared (by writing it to one). Further data reception will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions.
Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes.
219
2467X–AVR–06/11
ATmega128
Table 90. Status Codes for Slave Receiver Mode
Status Code |
|
|
Application Software Response |
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||
(TWSR) |
Status of the Two-wire Serial Bus |
|
To TWCR |
|
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|
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||
Prescaler Bits |
and Two-wire Serial |
Interface |
|
|
|
|
|
||
To/from TWDR |
STA |
|
STO |
TWINT |
TWEA |
|
|||
are 0 |
Hardware |
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|
Next Action Taken by TWI Hardware |
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$60 |
Own SLA+W has been received; |
No TWDR action or |
X |
|
0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
|
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ACK has been returned |
|
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|
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returned |
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No TWDR action |
X |
|
0 |
1 |
1 |
Data byte will be received and ACK will be returned |
$68 |
Arbitration lost in SLA+R/W as |
No TWDR action or |
X |
|
0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
|
|
master; own SLA+W has been |
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returned |
|
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received; ACK has been returned |
No TWDR action |
X |
|
0 |
1 |
1 |
Data byte will be received and ACK will be returned |
|
$70 |
General call address has been |
No TWDR action or |
X |
|
0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
|
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received; ACK has been returned |
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returned |
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No TWDR action |
X |
|
0 |
1 |
1 |
Data byte will be received and ACK will be returned |
$78 |
Arbitration lost in SLA+R/W as |
No TWDR action or |
X |
|
0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
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master; General call address has |
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returned |
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been received; ACK has been |
No TWDR action |
X |
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0 |
1 |
1 |
Data byte will be received and ACK will be returned |
|
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returned |
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$80 |
Previously addressed |
with own |
Read data byte or |
X |
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0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
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SLA+W; data has been received; |
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returned |
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ACK has been returned |
|
Read data byte |
X |
|
0 |
1 |
1 |
Data byte will be received and ACK will be returned |
$88 |
Previously addressed |
with own |
Read data byte or |
0 |
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0 |
1 |
0 |
Switched to the not addressed slave mode; |
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SLA+W; data has been received; |
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no recognition of own SLA or GCA |
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NOT ACK has been returned |
Read data byte or |
0 |
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0 |
1 |
1 |
Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1” |
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Read data byte or |
1 |
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0 |
1 |
0 |
Switched to the not addressed slave mode; |
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no recognition of own SLA or GCA; |
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a START condition will be transmitted when the bus |
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becomes free |
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Read data byte |
1 |
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0 |
1 |
1 |
Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1”; |
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a START condition will be transmitted when the bus |
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becomes free |
$90 |
Previously addressed with |
Read data byte or |
X |
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0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
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general call; data has been re- |
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returned |
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ceived; ACK has been returned |
Read data byte |
X |
|
0 |
1 |
1 |
Data byte will be received and ACK will be returned |
|
$98 |
Previously addressed with |
Read data byte or |
0 |
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0 |
1 |
0 |
Switched to the not addressed slave mode; |
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general call; data has been |
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no recognition of own SLA or GCA |
|
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received; NOT ACK has been |
Read data byte or |
0 |
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0 |
1 |
1 |
Switched to the not addressed slave mode; |
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returned |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1” |
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Read data byte or |
1 |
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0 |
1 |
0 |
Switched to the not addressed slave mode; |
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no recognition of own SLA or GCA; |
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a START condition will be transmitted when the bus |
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becomes free |
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Read data byte |
1 |
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0 |
1 |
1 |
Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1”; |
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a START condition will be transmitted when the bus |
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becomes free |
$A0 |
A STOP condition or repeated |
No Action |
0 |
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0 |
1 |
0 |
Switched to the not addressed slave mode; |
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START condition has been |
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no recognition of own SLA or GCA |
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received while still addressed as |
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0 |
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0 |
1 |
1 |
Switched to the not addressed slave mode; |
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slave |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1” |
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1 |
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0 |
1 |
0 |
Switched to the not addressed slave mode; |
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no recognition of own SLA or GCA; |
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a START condition will be transmitted when the bus |
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becomes free |
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1 |
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0 |
1 |
1 |
Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1”; |
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a START condition will be transmitted when the bus |
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becomes free |
220
2467X–AVR–06/11
ATmega128
Figure 101. Formats and States in the Slave Receiver Mode
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Reception of the |
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S |
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SLA |
W |
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A |
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DATA |
A |
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DATA |
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A |
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P or S |
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own slave address |
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and one or more |
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data bytes. All are |
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acknowledged |
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$60 |
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$80 |
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$80 |
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$A0 |
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Last data byte received |
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P or S |
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is not acknowledged |
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A |
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$88 |
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Arbitration lost as master |
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A |
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and addressed as slave |
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$68 |
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Reception of the general call |
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General Call |
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DATA |
A |
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DATA |
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P or S |
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address and one or more data |
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$70 |
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$90 |
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$90 |
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$A0 |
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Last data byte received is |
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P or S |
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not acknowledged |
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A |
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$98 |
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Arbitration lost as master and |
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A |
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addressed as slave by general call |
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$78 |
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Any number of data bytes |
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From master to slave |
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DATA |
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and their associated acknowledge bits |
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From slave to master |
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n |
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to a defined state of the Two-wire Serial Bus. The |
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prescaler bits are zero or masked to zero |
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Slave Transmitter |
In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver (see |
Mode |
Figure 102). All the status codes mentioned in this section assume that the prescaler bits are |
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zero or are masked to zero. |
Figure 102. Data Transfer in Slave Transmitter Mode
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VCC |
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Device 1 |
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Device 2 |
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Device 3 |
........ |
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Device n |
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R1 |
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SLAVE |
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TRANSMITTER |
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RECEIVER |
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SDA
SCL
To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:
221
2467X–AVR–06/11
ATmega128
TWAR |
TWA6 |
TWA5 |
TWA4 |
TWA3 |
TWA2 |
TWA1 |
TWA0 |
TWGCE |
value |
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Device’s Own Slave Address |
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The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore the general call address.
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
X |
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TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgment of the device’s own slave address or the general call address. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After its own slave address and the write bit have been received, the TWINT flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in Table 91. The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the Master mode (see state $B0).
If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the transfer. State $C0 or state $C8 will be entered, depending on whether the master receiver transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed slave mode, and will ignore the master if it continues the transfer. Thus the master receiver receives all “1” as serial data. State $C8 is entered if the master demands additional data bytes (by transmitting ACK), even though the slave has transmitted the last byte (TWEA zero and expecting NACK from the master).
While TWEA is zero, the TWI does not respond to its own slave address. However, the Two-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low during the wake up and until the TWINT flag is cleared (by writing it to one). Further data transmission will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions.
Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes.
222
2467X–AVR–06/11
ATmega128
Table 91. Status Codes for Slave Transmitter Mode
Status Code |
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Application Software Response |
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(TWSR) |
Status of the Two-wire Serial Bus |
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To TWCR |
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Prescaler Bits |
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To/from TWDR |
STA |
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STO |
TWINT |
TWEA |
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are 0 |
Hardware |
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Next Action Taken by TWI Hardware |
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$A8 |
Own SLA+R has been received; |
Load data byte or |
X |
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1 |
0 |
Last data byte will be transmitted and NOT ACK should |
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ACK has been returned |
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be received |
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Load data byte |
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Data byte will be transmitted and ACK should be re- |
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ceived |
$B0 |
Arbitration lost in SLA+R/W as |
Load data byte or |
X |
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0 |
Last data byte will be transmitted and NOT ACK should |
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master; own SLA+R has been |
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be received |
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received; ACK has been returned |
Load data byte |
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$B8 |
Data byte in TWDR has been |
Load data byte or |
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0 |
Last data byte will be transmitted and NOT ACK should |
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be received |
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received |
Load data byte |
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Data byte will be transmitted and ACK should be re- |
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ceived |
$C0 |
Data byte in TWDR has been |
No TWDR action or |
0 |
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Switched to the not addressed slave mode; |
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no recognition of own SLA or GCA |
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received |
No TWDR action or |
0 |
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1 |
1 |
Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1” |
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No TWDR action or |
1 |
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0 |
Switched to the not addressed slave mode; |
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no recognition of own SLA or GCA; |
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a START condition will be transmitted when the bus |
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becomes free |
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No TWDR action |
1 |
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Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1”; |
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a START condition will be transmitted when the bus |
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becomes free |
$C8 |
Last data byte in TWDR has been |
No TWDR action or |
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Switched to the not addressed slave mode; |
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no recognition of own SLA or GCA |
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has been received |
No TWDR action or |
0 |
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Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1” |
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No TWDR action or |
1 |
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Switched to the not addressed slave mode; |
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no recognition of own SLA or GCA; |
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a START condition will be transmitted when the bus |
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becomes free |
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No TWDR action |
1 |
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0 |
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Switched to the not addressed slave mode; |
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own SLA will be recognized; |
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GCA will be recognized if TWGCE = “1”; |
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a START condition will be transmitted when the bus |
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becomes free |
Figure 103. Formats and States in the Slave Transmitter Mode
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Reception of the |
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S |
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SLA |
R |
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DATA |
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and one or |
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more data bytes |
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$A8 |
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$B8 |
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$C0 |
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and addressed as slave |
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$B0 |
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Last data byte transmitted. |
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slave (TWEA = '0') |
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$C8 |
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Any number of data bytes |
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From master to slave |
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DATA |
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A |
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and their associated acknowledge bits |
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From slave to master |
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n |
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This number (contained in TWSR) corresponds |
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to a defined state of the Two-wire Serial Bus. The |
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prescaler bits are zero or masked to zero
223
2467X–AVR–06/11