- •Features
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
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- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
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- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
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- •Data Registers
- •Bypass Register
- •Reset Register
- •EXTEST; $0
- •IDCODE; $1
- •AVR_RESET; $C
- •BYPASS; $F
- •Scanning the ADC
- •ATmega128 Boundary-scan Order
- •Application Section
- •Programming Time for Flash when Using SPM
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
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- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
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- •Reset Register
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- •Electrical Characteristics
- •Absolute Maximum Ratings*
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- •Two-wire Serial Interface Characteristics
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- •Idle Supply Current
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- •Register Summary
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- •Packaging Information
- •Errata
- •ATmega128 Rev. F to M
ATmega128
Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 77 and Figure 78. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 70 and Table 71, as done below:
Table 73. CPOL and CPHA Functionality
|
Leading edge |
Trailing edge |
SPI mode |
|
|
|
|
CPOL = 0, CPHA = 0 |
Sample (Rising) |
Setup (Falling) |
0 |
|
|
|
|
CPOL = 0, CPHA = 1 |
Setup (Rising) |
Sample (Falling) |
1 |
|
|
|
|
CPOL = 1, CPHA = 0 |
Sample (Falling) |
Setup (Rising) |
2 |
|
|
|
|
CPOL = 1, CPHA = 1 |
Setup (Falling) |
Sample (Rising) |
3 |
|
|
|
|
Figure 77. SPI Transfer Format with CPHA = 0
SCK (CPOL = 0) mode 0
SCK (CPOL = 1) mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) |
MSB |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
LSB |
LSB first (DORD = 1) |
LSB |
Bit 1 |
Bit 2 |
Bit 3 |
Bit 4 |
Bit 5 |
Bit 6 |
MSB |
Figure 78. SPI Transfer Format with CPHA = 1
SCK (CPOL = 0) mode 1
SCK (CPOL = 1) mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) |
MSB |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
LSB |
LSB first (DORD = 1) |
LSB |
Bit 1 |
Bit 2 |
Bit 3 |
Bit 4 |
Bit 5 |
Bit 6 |
MSB |
169
2467X–AVR–06/11