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Table 103. Boundary-scan Signals for the Analog Comparator

Scanning the ADC Figure 131 shows a block diagram of the ADC with all relevant control and observe signals. The Boundary-scan cell from Figure 127 is attached to each of these signals. The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well.

Figure 131. Analog to Digital Converter

The signals are described briefly in Table 104.

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Table 104. Boundary-scan Signals for the ADC

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Note: Incorrect setting of the switches in Figure 131 will make signal contention and may damage the part. There are several input choices to the S&H circuitry on the negative input of the output comparator in Figure 131. Make sure only one path is selected from either one ADC pin, Bandgap reference source, or Ground.

If the ADC is not to be used during scan, the recommended input values from Table 104 should be used. The user is recommended not to use the Differential Gain stages during scan. SwitchCap based gain stages require fast operation and accurate timing which is difficult to obtain when used in a scan chain. Details concerning operations of the differential gain stage is therefore not provided.

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The Atmel® AVR® ADC is based on the analog circuitry shown in Figure 131 with a successive approximation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is usually to ensure that an applied analog voltage is measured within some limits. This can easily be done without running a successive approximation algorithm: apply the lower limit on the digital DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit on the digital DAC[9:0] lines, and verify the output from the comparator to be high.

The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well.

When using the ADC, remember the following

•The Port Pin for the ADC channel in use must be configured to be an input with pull-up disabled to avoid signal contention.

•In normal mode, a dummy conversion (consisting of 10 comparisons) is performed when enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before controlling/observing any ADC signal, or perform a dummy conversion before using the first result.

•The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low (Sample mode).

As an example, consider the task of verifying a 1.5V ±5% input signal at ADC channel 3 when the power supply is 5.0V and AREF is externally connected to VCC.

The recommended values from Table 104 are used unless other values are given in the algorithm in Table 105. Only the DAC and Port Pin values of the Scan Chain are shown. The column “Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register with the succeeding columns. The verification should be done on the data scanned out when scanning in the data on the same row in the table.

Table 105. Algorithm for Using the ADC

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Table 105. Algorithm for Using the ADC

Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock frequency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at least five times the number of scan bits divided by the maximum hold time, thold,max

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