- •Features
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •Resources
- •Data Retention
- •Capacitive touch sensing
- •AVR CPU Core
- •Introduction
- •Status Register
- •Stack Pointer
- •I/O Memory
- •Overview
- •Timing
- •Using all Locations of External Memory Smaller than 64 Kbyte
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Register Description for I/O Ports
- •8-bit Timer/Counter0 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Noise Canceler
- •Force Output Compare
- •Normal Mode
- •Fast PWM Mode
- •16-bit Timer/Counter Register Description
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter2 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Output Compare Modulator (OCM1C2)
- •Overview
- •Description
- •Timing Example
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Dual USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Frame Formats
- •Parity Bit Calculation
- •Parity Generator
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Using MPCM
- •Features
- •TWI Terminology
- •Transferring Bits
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •Scl and SDA Pins
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •Using the TWI
- •Master Receiver Mode
- •Slave Receiver Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •Analog Input Circuitry
- •Features
- •Overview
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Reset Register
- •EXTEST; $0
- •IDCODE; $1
- •AVR_RESET; $C
- •BYPASS; $F
- •Scanning the ADC
- •ATmega128 Boundary-scan Order
- •Application Section
- •Programming Time for Flash when Using SPM
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Programming Command Register
- •Virtual Flash Page Read Register
- •Performing Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •Speed Grades
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics
- •External Data Memory Timing
- •Idle Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega128 Rev. F to M
ATmega128
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Table 116. |
Lock Bit Protection Modes (Continued) |
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Memory Lock Bits |
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Protection Type |
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1 |
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1 |
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1 |
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No restrictions for SPM or (E)LPM accessing the Boot |
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Loader section. |
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2 |
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1 |
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0 |
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SPM is not allowed to write to the Boot Loader section. |
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SPM is not allowed to write to the Boot Loader section, |
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and (E)LPM executing from the Application section is not |
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3 |
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0 |
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0 |
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allowed to read from the Boot Loader section. If interrupt |
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vectors are placed in the Application section, interrupts |
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are disabled while executing from the Boot Loader section. |
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(E)LPM executing from the Application section is not |
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4 |
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0 |
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allowed to read from the Boot Loader section. If interrupt |
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vectors are placed in the Application section, interrupts |
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are disabled while executing from the Boot Loader section. |
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Notes: 1. Program the fuse bits before programming the Lock bits. |
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2. “1” means unprogrammed, “0´means programmed |
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Fuse Bits |
The Atmel® AVR®ATmega128 has three fuse bytes. Table 117 - Table 119 describe briefly the |
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functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses |
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are read as logical zero, “0”, if they are programmed. |
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Table 117. Extended Fuse Byte |
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Extended Fuse Byte |
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Bit No. |
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Description |
Default Value |
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– |
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7 |
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– |
1 |
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– |
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6 |
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– |
1 |
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– |
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5 |
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– |
1 |
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– |
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4 |
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– |
1 |
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– |
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3 |
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– |
1 |
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– |
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2 |
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– |
1 |
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M103C(1) |
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1 |
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ATmega103 compatibility mode |
0 |
(programmed) |
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WDTON(2) |
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0 |
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Watchdog Timer always on |
1 |
(unprogrammed) |
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Notes: 1. See “ATmega103 and ATmega128 Compatibility” on page 4 for details. |
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2. See “Watchdog Timer Control Register – WDTCR” on page 55 for details. |
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ATmega128
Table 118. Fuse High Byte
Fuse High |
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Byte |
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Bit No. |
Description |
Default Value |
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OCDEN(4) |
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7 |
Enable OCD |
1 |
(unprogrammed, OCD |
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disabled) |
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JTAGEN(5) |
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6 |
Enable JTAG |
0 |
(programmed, JTAG enabled) |
SPIEN(1) |
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5 |
Enable Serial Program and |
0 |
(programmed, SPI prog. |
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Data Downloading |
enabled) |
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CKOPT(2) |
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4 |
Oscillator options |
1 (unprogrammed) |
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EESAVE |
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3 |
EEPROM memory is preserved |
1 |
(unprogrammed, EEPROM not |
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through the Chip Erase |
preserved) |
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BOOTSZ1 |
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2 |
Select Boot Size (see Table 112 |
0 |
(programmed)(3) |
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for details) |
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BOOTSZ0 |
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1 |
Select Boot Size (see Table 112 |
0 |
(programmed)(3) |
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for details) |
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BOOTRST |
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0 |
Select Reset Vector |
1 (unprogrammed) |
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Notes: 1. |
The SPIEN fuse is not accessible in SPI Serial Programming mode. |
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2.The CKOPT fuse functionality depends on the setting of the CKSEL bits. See “Clock Sources” on page 36 for details.
3.The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 112 on page 284
4.Never ship a product with the OCDEN Fuse programmed regardless of the setting of lock bits and the JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to be running in all sleep modes. This may increase the power consumption.
5.If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be disabled. This
to avoid static current at the TDO pin in the JTAG interface.
Table 119. Fuse Low Byte
Fuse Low |
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Bit No. |
Description |
Default Value |
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BODLEVEL |
7 |
Brown out detector trigger level |
1 |
(unprogrammed) |
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BODEN |
6 |
Brown out detector enable |
1 |
(unprogrammed, BOD disabled) |
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SUT1 |
5 |
Select start-up time |
1 |
(unprogrammed)(1) |
SUT0 |
4 |
Select start-up time |
0 |
(programmed)(1) |
CKSEL3 |
3 |
Select Clock source |
0 |
(programmed)(2) |
CKSEL2 |
2 |
Select Clock source |
0 |
(programmed)(2) |
CKSEL1 |
1 |
Select Clock source |
0 |
(programmed)(2) |
CKSEL0 |
0 |
Select Clock source |
1 (unprogrammed)(2) |
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Notes: 1. The default value of SUT1..0 results in maximum start-up time. See Table 14 on page 41 for details.
2.The default setting of CKSEL3..0 results in Internal RC Oscillator @ 1MHz. See Table 6 on page 36 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
Latching of Fuses The Fuse values are latched when the device enters Programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to
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