Добавил:

Upload Опубликованный материал нарушает ваши авторские права? Сообщите нам.

Вуз:

Санкт-Петербургский государственный электротехнический университет "ЛЭТИ"

Предмет:

[НЕСОРТИРОВАННОЕ]

Файл:

ATmega128 datasheet.pdf

Скачиваний:

Добавлен:

09.02.2015

Размер:

6.34 Mб

Скачать

☆

<<< < Предыдущая 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 6364 / 6964 65 66 67 68 69 > Следующая >>>

ATmega128

External Data Memory Timing

Table 137. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state

				8MHz Oscillator		Variable Oscillator

	Symbol		Parameter	Min	Max	Min		Max		Unit

0	1/tCLCL		Oscillator Frequency			0.0		16		MHz
1	tLHLL		ALE Pulse Width	115		1.0tCLCL-10
2	t	AVLL	Address Valid A to ALE Low	57.5		0.5t	-5(1)
		AVLL				CLCL
			Address Hold After ALE Low,	5		5
3a	tLLAX_ST		write access	5		5
3a	tLLAX_ST		write access
			Address Hold after ALE Low,	5		5
3b	tLLAX_LD		read access	5		5
3b	tLLAX_LD		read access
4	t	AVLLC	Address Valid C to ALE Low	57.5		0.5t	-5(1)
		AVLLC				CLCL
5	tAVRL		Address Valid to RD Low	115		1.0tCLCL-10
6	tAVWL		Address Valid to WR Low	115		1.0tCLCL-10
7	t	LLWL	ALE Low to WR Low	47.5	67.5	0.5t	-15(2)	0.5t	+5(2)
		LLWL				CLCL		CLCL		ns
8	t	LLRL	ALE Low to RD Low	47.5	67.5	0.5t	-15(2)	0.5t	+5(2)	ns
8	t		ALE Low to RD Low	47.5	67.5	0.5t	-15(2)	0.5t	+5(2)
						CLCL		CLCL
9	tDVRH		Data Setup to RD High	40		40
10	tRLDV		Read Low to Data Valid		75			1.0tCLCL-50
11	tRHDX		Data Hold After RD High	0		0
12	tRLRH		RD Pulse Width	115		1.0tCLCL-10
13	t	DVWL	Data Setup to WR Low	42.5		0.5t	-20(1)
		DVWL				CLCL
14	tWHDX		Data Hold After WR High	115		1.0tCLCL-10
15	tDVWH		Data Valid to WR High	125		1.0tCLCL
16	tWLWH		WR Pulse Width	115		1.0tCLCL-10

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 138. External Data Memory Characteristics, 4.5 - 5.5V, 1 Cycle Wait-state

			8MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	16	MHz
10	tRLDV	Read Low to Data Valid		200		2.0tCLCL-50
12	tRLRH	RD Pulse Width	240		2.0tCLCL-10		ns
15	tDVWH	Data Valid to WR High	240		2.0tCLCL		ns
15	tDVWH	Data Valid to WR High	240		2.0tCLCL
16	tWLWH	WR Pulse Width	240		2.0tCLCL-10

328

2467X–AVR–06/11

ATmega128

Table 139. External Data Memory Characteristics, 4.5 - 5.5V, SRWn1 = 1, SRWn0 = 0

			4MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	16	MHz
10	tRLDV	Read Low to Data Valid		325		3.0tCLCL-50
12	tRLRH	RD Pulse Width	365		3.0tCLCL-10		ns
15	tDVWH	Data Valid to WR High	375		3.0tCLCL		ns
15	tDVWH	Data Valid to WR High	375		3.0tCLCL
16	tWLWH	WR Pulse Width	365		3.0tCLCL-10

Table 140. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

			4MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	16	MHz
10	tRLDV	Read Low to Data Valid		325		3.0tCLCL-50
12	tRLRH	RD Pulse Width	365		3.0tCLCL-10
14	tWHDX	Data Hold After WR High	240		2.0tCLCL-10		ns
15	tDVWH	Data Valid to WR High	375		3.0tCLCL
16	tWLWH	WR Pulse Width	365		3.0tCLCL-10

Table 141. External Data Memory Characteristics, 2.7 - 5.5V, No Wait-state

			4MHz Oscillator			Variable Oscillator

	Symbol	Parameter	Min	Max		Min	Max		Unit

0	1/tCLCL	Oscillator Frequency				0.0	8		MHz
1	tLHLL	ALE Pulse Width	235		tCLCL-15
2	t	Address Valid A to ALE Low	115		0.5t	-10(1)
	AVLL					CLCL
		Address Hold After ALE Low,	5			5
3a	tLLAX_ST	write access	5			5
3a	tLLAX_ST	write access
		Address Hold after ALE Low,	5			5
3b	tLLAX_LD	read access	5			5
3b	tLLAX_LD	read access
4	t	Address Valid C to ALE Low	115		0.5t	-10(1)
	AVLLC					CLCL
5	tAVRL	Address Valid to RD Low	235		1.0tCLCL-15				ns
6	tAVWL	Address Valid to WR Low	235		1.0tCLCL-15
7	t	ALE Low to WR Low	115	130	0.5t	-10(2)	0.5t	+5(2)
	LLWL					CLCL	CLCL
8	t	ALE Low to RD Low	115	130	0.5t	-10(2)	0.5t	+5(2)
	LLRL					CLCL	CLCL
9	tDVRH	Data Setup to RD High	45			45
10	tRLDV	Read Low to Data Valid		190			1.0tCLCL-60
11	tRHDX	Data Hold After RD High	0			0

329

2467X–AVR–06/11

ATmega128

Table 141. External Data Memory Characteristics, 2.7 - 5.5V, No Wait-state					(Continued)
			4MHz Oscillator			Variable Oscillator

	Symbol	Parameter	Min	Max		Min	Max	Unit

12	tRLRH	RD Pulse Width	235			1.0tCLCL-15
13	t	Data Setup to WR Low	105			0.5t -20(1)
	DVWL					CLCL
14	tWHDX	Data Hold After WR High	235			1.0tCLCL-15		ns
15	tDVWH	Data Valid to WR High	250			1.0tCLCL
16	tWLWH	WR Pulse Width	235			1.0tCLCL-15

Table 142. External Data Memory Characteristics, 2.7 - 5.5V, SRWn1 = 0, SRWn0 = 1
			4MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	8	MHz
10	tRLDV	Read Low to Data Valid		440		2.0tCLCL-60
12	tRLRH	RD Pulse Width	485		2.0tCLCL-15		ns
15	tDVWH	Data Valid to WR High	500		2.0tCLCL		ns
15	tDVWH	Data Valid to WR High	500		2.0tCLCL
16	tWLWH	WR Pulse Width	485		2.0tCLCL-15

Table 143. External Data Memory Characteristics, 2.7 - 5.5V, SRWn1 = 1, SRWn0 = 0

			4MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	8	MHz
10	tRLDV	Read Low to Data Valid		690		3.0tCLCL-60
12	tRLRH	RD Pulse Width	735		3.0tCLCL-15		ns
15	tDVWH	Data Valid to WR High	750		3.0tCLCL		ns
15	tDVWH	Data Valid to WR High	750		3.0tCLCL
16	tWLWH	WR Pulse Width	735		3.0tCLCL-15

Table 144. External Data Memory Characteristics, 2.7 - 5.5V, SRWn1 = 1, SRWn0 = 1

			4MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	8	MHz
10	tRLDV	Read Low to Data Valid		690		3.0tCLCL-60
12	tRLRH	RD Pulse Width	735		3.0tCLCL-15
14	tWHDX	Data Hold After WR High	485		2.0tCLCL-15		ns
15	tDVWH	Data Valid to WR High	750		3.0tCLCL
16	tWLWH	WR Pulse Width	735		3.0tCLCL-15

330

2467X–AVR–06/11

ATmega128

Figure 157. External Memory Timing (SRWn1 = 0, SRWn0 = 0

	T1	T2		T3	T4
System Clock (CLKCPU)
		1
ALE
		4	7
A15:8	Prev. addr.			Address
				15
		2	3a	13
DA7:0	Prev. data	Address	XX	Data
		6		16	14
		6		16
WR
			3b	9	11
DA7:0 (XMBK = 0)		Address		Data
		5		10
			8	12

Figure 158. External Memory Timing (SRWn1 = 0, SRWn0 = 1)

	T1	T2		T3	T4	T5
System Clock (CLKCPU)
		1
ALE
		4	7
A15:8	Prev. addr.			Address
					15
		2	3a	13
DA7:0	Prev. data	Address	XX		Data
		6			16	14
		6			16
WR
			3b		9	11
DA7:0 (XMBK = 0)		Address			Data
		5		10
			8		12

Write

Read

Write

Read

331

2467X–AVR–06/11

ATmega128

Figure 159. External Memory Timing (SRWn1 = 1, SRWn0 = 0)

	T1	T2		T3	T4	T5	T6
System Clock (CLKCPU)
		1
ALE
		4	7
A15:8	Prev. addr.				Address
					15
		2	3a	13
DA7:0	Prev. data	Address	XX		Data
		6			16		14
					16

WR
			3b		9		11
DA7:0 (XMBK = 0)		Address			Data
		5		10
			8		12

Write

Read

Figure 160. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1)

	T1	T2		T3	T4	T5	T6	T7
System Clock (CLKCPU)
		1
ALE
		4	7
A15:8	Prev. addr.				Address
					15
		2	3a	13
DA7:0	Prev. data	Address	XX		Data
		6			16			14
					16

WR
			3b		9		11
DA7:0 (XMBK = 0)		Address			Data
		5		10
			8		12

Read Write

Note: 1. The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal or external).

332

2467X–AVR–06/11

ATmega128

Typical

Characteristics

The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.

Active Supply Current Figure 161. Active Supply Current vs. Frequency (0.1 - 1.0MHz)

	3.5
	3										5.5V
	3
											5.0V
	2.5										4.5V
											4.0V
(mA)	2										3.3V
	2										2.7V
											2.7V

CC	1.5
I

	1
	0.5
	0
	0	0.1	0.2	0.3	0.4	0.5	0.6	0.7	0.8	0.9	1

Frequency (MHz)

333

2467X–AVR–06/11

ATmega128

Figure 162. Active Supply Current vs. Frequency (1 - 20MHz)

	45
	40										5.0V
	35										4.5V
	30
(mA)	25
(mA)
CC	20							4.0V
I	20

	15						3.6V
						3.3V	3.6V
	10					3.3V
	10					3.0V
						3.0V
	5					2.7V
	5
	0
	0	2	4	6	8	10	12	14	16	18	20

Frequency (MHz)

Figure 163. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)

4
						25	°C
3.5						-40	°C
3.5						85	°C
						85	°C
3
(mA)
CC
I
2.5
2
1.5
2.5	3	3.5	4	4.5	5	5.5

VCC (V)

334

2467X–AVR–06/11

ATmega128

Figure 164. Active Supply Current vs. VCC (Internal RC Oscillator, 2MHz)

	8
							-40 °C
	7						25 °C
	6						85 °C
	6
	5
(mA)	4
CC
I
	3
	2
	1
	0
	2.5	3	3.5	4	4.5	5	5.5

VCC (V)

Figure 165. Active Supply Current vs. VCC (Internal RC Oscillator, 4MHz)

	14
	12						-40	°C
	12						25	°C
							85	°C
	10
(mA)	8
(mA)
CC	6
I

	4
	2
	0
	2.5	3	3.5	4	4.5	5	5.5

VCC (V)

335

2467X–AVR–06/11

ATmega128

Figure 166. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)

25
						-40	°C
						25	°C
20						85	°C
15
(mA)
CC
I
10
5
0
2.5	3	3.5	4	4.5	5	5.5

VCC (V)

Figure 167. Active Supply Current vs. VCC (32kHz External Oscillator)

	140
	120						25 °C
							25 °C
	100
ICC (uA)	80
ICC (uA)	60
	60
	40
	20
	0
	2.5	3	3.5	4	4.5	5	5.5

VCC (V)

336

2467X–AVR–06/11

<<< < Предыдущая 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 6364 / 6964 65 66 67 68 69 > Следующая >>>

Соседние файлы в предмете [НЕСОРТИРОВАННОЕ]

#
09.02.2015140.8 Кб36Antennas_2.doc
#
09.02.2015305.15 Кб44antennas_3.doc
#
09.02.2015586.24 Кб34Antenns_Gl02_02.doc
#
22.11.20181.67 Mб62Arhitektura_EVM.doc
#
07.09.2019108.49 Кб6Article 1.docx
#
09.02.20156.34 Mб12ATmega128 datasheet.pdf
#
09.02.2015598.26 Кб12atmega128 summary.pdf
#
09.02.20151.29 Mб8Atmel_AVRInstructioSet.pdf
#
09.02.2015396.72 Кб13AVL-деревья.pdf
#
09.02.2015147.22 Кб9AVLTree - wikipedia.pdf
#
09.02.20151.24 Mб7AVS Kurs Method (2008) (NEW).doc