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WD_EEPROM

ATmega128

3.The SPI Serial Programming instructions will not work if the communication is out of synchronization. When in sync. the second byte ($53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all FOUR bytes of the instruction must be transmitted. If the $53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command.

4.The Flash is programmed one page at a time. The page size is found in Table 124 on page 291. The memory page is loaded one byte at a time by supplying the 7 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 9MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 128).

Note: If other commands than polling (read) are applied before any write operation (Flash, EEPROM, Lock bits, Fuses) is completed, may result in incorrect programming.

5.The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait

at least tWD_EEPROM before issuing the next byte. (See Table 128). In a chip erased device, no $FFs in the data file(s) need to be programmed.

6.Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO.

7.At the end of the programming session, RESET can be set high to commence normal operation.

8.Power-off sequence (if needed): Set RESET to “1”.

Turn VCC power off.

Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value $FF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value $FF, so when programming

this value, the user will have to wait for at least tWD_FLASH before programming the next page. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to

contain $FF, can be skipped. See Table 128 for tWD_FLASH value

Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $FF, but the user should have the following in mind: As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF, can be skipped. This does not apply if the EEPROM is re-programmed without chip-erasing the device. In this case, data polling cannot be used for the value $FF, and the user will have to wait at least t before programming the next byte. See Table 128 for tWD_EEPROM value.

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Table 128. Minimum Wait Delay before Writing the Next Flash or EEPROM Location, VCC = 5V ±10%

Symbol

Minimum Wait Delay

 

 

tWD_FUSE

4.5ms

tWD_FLASH

5ms

tWD_EEPROM

10ms

tWD_ERASE

10ms

Figure 145. .SPI Serial Programming Waveforms

SERIAL DATA INPUT

MSB

LSB

(MOSI)

 

 

SERIAL DATA OUTPUT

MSB

LSB

(MISO)

 

 

SERIAL CLOCK INPUT

 

 

(SCK)

 

 

SAMPLE

 

 

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Table 129. SPI Serial Programming Instruction Set

 

 

Instruction Format

 

 

 

 

 

 

 

 

 

 

Instruction

Byte 1

Byte 2

Byte 3

Byte 4

Operation

 

 

 

 

 

 

 

 

Programming Enable

1010 1100

0101 0011

xxxx xxxx

xxxx xxxx

Enable SPI Serial Programming after

 

 

RESET

 

 

 

 

 

goes low.

 

 

 

 

 

 

Chip Erase

1010 1100

100x xxxx

xxxx xxxx

xxxx xxxx

Chip Erase EEPROM and Flash.

 

 

 

 

 

 

Read Program

0010 H000

aaaa aaaa

bbbb bbbb

oooo oooo

Read H (high or low) data o from Program

Memory

 

 

 

 

memory at word address a:b.

 

 

 

 

 

 

Load Program

0100 H000

xxxx xxxx

xbbb bbbb

iiii iiii

Write H (high or low) data i to Program

Memory Page

 

 

 

 

Memory page at word address b. Data low

 

 

 

 

 

byte must be loaded before data high byte is

 

 

 

 

 

applied within the same address.

 

 

 

 

 

 

 

 

Write Program

0100 1100

aaaa aaaa

bxxx xxxx

xxxx xxxx

 

 

 

Memory Page

 

 

 

 

Write Program Memory Page at address a:b.

 

 

 

 

 

 

Read EEPROM

1010 0000

xxxx aaaa

bbbb bbbb

oooo oooo

Read data o from EEPROM memory at

Memory

 

 

 

 

address a:b.

 

 

 

 

 

 

Write EEPROM

1100 0000

xxxx aaaa

bbbb bbbb

iiii iiii

Write data i to EEPROM memory at address

Memory

 

 

 

 

a:b.

 

 

 

 

 

 

Read Lock bits

0101 1000

0000 0000

xxxx xxxx

xxoo oooo

Read Lock bits. “0” = programmed, “1” =

 

 

 

 

 

unprogrammed. See Table 115 on page

 

 

 

 

 

286 for details.

 

 

 

 

 

 

Write Lock bits

1010 1100

111x xxxx

xxxx xxxx

11ii iiii

Write Lock bits. Set bits = “0” to program Lock

 

 

 

 

 

bits. See Table 115 on page 286 for details.

 

 

 

 

 

 

Read Signature Byte

0011 0000

xxxx xxxx

xxxx xxbb

oooo oooo

Read Signature Byte o at address b.

 

 

 

 

 

 

Write Fuse bits

1010 1100

1010 0000

xxxx xxxx

iiii iiii

Set bits = “0” to program, “1” to unprogram.

 

 

 

 

 

See Table 119 on page 288 for details.

 

 

 

 

 

 

Write Fuse High Bits

1010 1100

1010 1000

xxxx xxxx

iiii iiii

Set bits = “0” to program, “1” to unprogram.

 

 

 

 

 

See Table 118 on page 288 for details.

 

 

 

 

 

 

Write Extended Fuse

1010 1100

1010 0100

xxxx xxxx

xxxx xxii

Set bits = “0” to program, “1” to unprogram.

bits

 

 

 

 

See Table 119 on page 288 for details.

 

 

 

 

 

 

Read Fuse bits

0101 0000

0000 0000

xxxx xxxx

oooo oooo

Read Fuse bits. “0” = programmed, “1” =

 

 

 

 

 

unprogrammed. See Table 119 on page

 

 

 

 

 

288 for details.

 

 

 

 

 

 

Read Extendend

0101 0000

0000 1000

xxxx xxxx

oooo oooo

Read Extended Fuse bits. “0” = pro-grammed,

Fuse bits

 

 

 

 

“1” = unprogrammed. See Table 119 on

 

 

 

 

 

page 288 for details.

 

 

 

 

 

 

Read Fuse High Bits

0101 1000

0000 1000

xxxx xxxx

oooo oooo

Read Fuse high bits. “0” = pro-grammed, “1” =

 

 

 

 

 

unprogrammed. See Table 118 on page

 

 

 

 

 

288 for details.

 

 

 

 

 

 

Read Calibration Byte

0011 1000

xxxx xxxx

0000 00bb

oooo oooo

Read Calibration Byte o at address b.

 

 

 

 

 

 

 

 

Note: a = address high bits b = address low bits

H = 0 - Low byte, 1 - High Byte o = data out

i = data in

x = don’t care

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SPI Serial

For characteristics of the SPI module, see “SPI Timing Characteristics” on page 323.

Programming

 

Characteristics

 

Programming Via

Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,

the JTAG Interface

TMS, TDI, and TDO. Control of the Reset and clock pins is not required.

 

To be able to use the JTAG interface, the JTAGEN fuse must be programmed. The device is

 

default shipped with the Fuse programmed. In addition, the JTD bit in MCUCSR must be

 

cleared. Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit

 

will be cleared after two chip clocks, and the JTAG pins are available for programming. This pro-

 

vides a means of using the JTAG pins as normal port pins in running mode while still allowing In-

 

System Programming via the JTAG interface. Note that this technique can not be used when

 

using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must

 

be dedicated for this purpose.

 

As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers.

Programming Specific

The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions

JTAG Instructions

useful for Programming are listed below.

 

The OPCODE for each instruction is shown behind the instruction name in hex format. The text

 

describes which data register is selected as path between TDI and TDO for each instruction.

 

The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be

 

used as an idle state between JTAG sequences. The state machine sequence for changing the

 

instruction word is shown in Figure 146.

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