USB System Architecture

High-Speed Differential Signaling

High-speed differential signaling is performed using high-speed current drivers and high-speed receivers. The high-speed environment also seeks to eliminate the effects of standing waves (reflections). These reflections occur if the traces are not terminated to match the characteristic impedance of the cable during the 480Mb/s differential signaling.

Impedance Matching

Impedance matching during high-speed differential signaling eliminates unwanted signal reflections by matching the 90Ω differential impedance of the cable with two 45Ω terminators in series between the data lines. This is accomplished when the full-speed drivers signal SE0 (drive both lines low). The output impedance of the driver must be controlled so that when the driver is “on,” a 45Ω impedance is seen between each data line and ground. The resulting 90 Ω differential termination yields a reflection coefficient of zero.

The specification recommends the use of a CMOS buffer with a low output impedance and a series resistor that combine to form an impedance of 45Ω at one end of the trace. The full-speed driver in the hub and the full-speed driver in the device functionally become terminators, each of which contributes half of the required 90Ω termination. Figure 11-5 on page 225 illustrates this implementation.

The specification requires the output impedance of the full-speed drivers to be controlled within 45Ω ± 10% (40.5 to 49.5Ω ) for all transceivers that are high speed capable. The specification also specifies that the full-speed drivers must have an output impedance within the range of 28Ω to 44Ω for devices that are not high speed capable. Since high-speed devices are required to operate in both full-speed and high-speed signaling environments, it is interesting to note that high-speed capable devices will be out of tolerance relative to full-speed- only transceiver specification. The specification makes no reference to this difference; thus, it is the interpretation of the author that when a HS capable device is operating in full-speed mode, the possible 5.5Ω difference in allowed output impedance will not create problems during full-speed signaling.

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Chapter 11: The High-Speed Signaling Environment

Figure 11-5: High-Speed Cable Termination

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USB System Architecture

High-Speed Driver Characteristics

Transmission of high-speed data is like fullor low-speed data transmission in that the data stream is NRZI encoded and signaled differentially across the cable. Differential transitions indicate a logic “0” is being transferred, while no transition during a given bit time indicates a logic “1.” Similarly, differential signal states are referred to as J and K states as in the lowand full-speed signaling environment.

Figure 11-6 depicts the essential elements for high-speed differential signaling. High-speed signaling is accomplished via a current driver that directs current to the D+ or D- lines to signal high-speed J and high-speed K respectively. The current is nominally 17.78mA and flows through a 22.5Ω load (two 45Ω terminations in parallel) to ground. This creates a differential voltage of approximately ±400mV depending on whether the current is directed to D+ or D-.

Figure 11-6: Interface Elements Used During High-Speed Differential Signaling

The specification recommends that the high-speed driver remain disabled until signaling begins, but recognizes the difficulty in meeting the timing and amplitude specifications when starting packet transmission without dropping the first bit. Therefore, the specification allows a less power-efficient solution where the driver can remain on and direct current to ground when no signaling is being performed. Figure 11-6 illustrates a current driver with inputs labeled HS Current (Curr) Enable, HS Drive (Drv) Enable, and HS Transmit (Xmt) Data.

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Chapter 11: The High-Speed Signaling Environment

The HS Current Enable input in this example activates the current driver, while the HS Drive Enable directs current to ground when no signaling is being performed. Differential signaling is performed by disabling HS Drive Enable and toggling the HS Xmt Data input, which directs current into either the D+ or D- lines.

High-Speed Idle

Figure 11-6 on page 226 makes clear the state of the bus when there is no signaling across the bus. In this case both D+ and D- will be held low by the 45Ω terminators at the end of each trace, indicating bus idle. The high-speed bus normally remains idle for only short periods (no longer than 125µ s). The greatest amount of bus idle occurs when there are no high-speed transactions being performed. Even under these conditions, the host transmits a high-speed micro Start of Frame (µ SOF) packet at the beginning of each µ frame (at 125µ s intervals). This packet is transferred to all enabled high-speed ports, thus ensuring that high-speed devices detect periodic bus activity. However, longer periods of bus idle may occur for several reasons:

1.µ SOF packets may be missed, causing maximum bus idle time to extend beyond 125µ s.

2.The device may be reset, which is signaled via a SE0 for 10ms to 20ms.

3.The device may be suspended, which is indicated by >3ms of bus idle.

High-Speed Differential Receivers

The high-speed differential receiver remains inactive (squelched) while the bus is idle and until the start of packet is detected. This prevents the receiver from inadvertently detecting noise on the cable in this low voltage signaling environment. Figure 11-7 on page 228 highlights the differential envelope detector that activates the high-speed differential receiver. A delay of up to four clocks may exist from envelope detection to receiver enable. This delay is not significant because every packet begins with a synchronization sequence and the loss of four clocks from this sequence is not critical.

Note that receiver electrical characteristics are defined by eye diagrams. See “Eye Pattern Tests” on page 231.

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